Semiconductor device including a semiconductor chip mounted...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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C257SE23026, C257SE23044, C257SE23124, C257SE23135, C257SE23052, C257S708000, C257S107000, C257S689000, C257S730000, C257S732000, C257S731000, C257S688000, C257S690000, C257S692000, C361S760000, C361S749000, C361S777000, C361S776000

Reexamination Certificate

active

10946733

ABSTRACT:
A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portions (12) with connection electrodes (15A) having a surface level higher than that of electrodes (7and8) on a surface of the semiconductor chip (1) by a difference (d). The connection electrode (15A) can be formed on a projecting piece (16) that is bent outward away from remaining portions of the side portion (12). The semiconductor device can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7and8) and the mounting substrate, thereby raising the reliability of the soldering connection.

REFERENCES:
patent: 3412788 (1968-11-01), Pomerantz
patent: 6853066 (2005-02-01), Hosoya
patent: 6992386 (2006-01-01), Hata et al.
patent: 2004/0021216 (2004-02-01), Hosoya
patent: 2004/0065462 (2004-04-01), Hayashi
patent: 2000-277542 (2000-10-01), None
patent: 2001-68503 (2001-03-01), None
patent: 2001-352009 (2001-12-01), None
patent: 2002-26067 (2002-01-01), None
Japanese Patent Office Action of Dec. 8, 2005.
English Translations of the indicated portions of the above-referenced Japanese Office Action.
U.S. Appl. No. 10/613,903, filed Feb. 5, 2004, Hosoya.

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