Semiconductor device including a JFET having a short-circuit...

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor

Reexamination Certificate

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C257S256000, C257S272000

Reexamination Certificate

active

07994535

ABSTRACT:
To improve the surge resistance of J-FET, a P-type epitaxial layer2and an N-type epitaxial layer3are formed on a P++-conductive substrate1; N+-conductive source diffusion layer4and drain diffusion layer5, and a p+-conductive gate diffusion layer6are formed in the N-type epitaxial layer3; and a short-circuit preventing layer8of a reversed conduction-type diffusion layer is formed adjacent to the side walls of the source diffusion layer4and the drain diffusion layer5. Having the constitution, the punch-through to be caused by surge voltage is prevented in the surface region of the device, and the surge resistance thereof is improved. Via the holes formed in a protective insulation film9on the surface of the device, a source electrode10connected to the source diffusion layer4, and a drain electrode11connected to the drain diffusion layer5are formed on the surface side of the device. A gate electrode12is formed on the back of the substrate1, and this is connected to the gate diffusion layer6via a contact diffusion layer7formed in the device.

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patent: 11162993 (1999-06-01), None
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Japanese Office Action, with English translation, issued in Japanese Patent Application No. 2003-154865, mailed Jul. 14, 2009.

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