Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2002-04-08
2002-11-26
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S271000, C327S269000, C327S284000
Reexamination Certificate
active
06486722
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a control signal generation circuit, and more particularly to a favorable structure of the control signal generation circuit for generating an internal control signal of a semiconductor device.
2. Description of the Background Art
In semiconductor devices including memory devices, generally a circuit supplying a control signal as an output is provided for the generation of an internal control signal which is employed for the control of a series of internal operations sequentially performed at a predetermined timing.
In a control signal generation circuit in a DRAM (Dynamic Random Access Memory), for example, first, command control signals such as /RAS, /CAS and /WE signals are supplied from an external source, then a command is generated according to the combination thereof, and a plurality of internal control signals are sequentially activated for carrying out a series of operations corresponding to the command.
FIG. 14
is a circuit diagram showing a structure of a control signal generation circuit
510
which is an example of a control circuit for generating a read command in the DRAM.
With reference to
FIG. 14
, control signal generation circuit
510
includes a logic gate LG
50
supplying the result of an AND operation as an output according to the combination of signal levels of command control signals such as /RAS, /CAS, and so on supplied as inputs, a logic gate LG
52
supplying the result of an OR operation of the output results from logic gates LG
50
and LG
54
, and an edge trigger flip flop
515
taking in the output of logic gate LG
52
in response to the rising edge of a clock signal CLK and determining the signal level of a read command signal READ.
Read command signal READ is activated (to an H level) when the read command is designated. A burst operation end signal /BSTEND is a signal which is set to an H level at the start of the reading operation and set to an L level at the end of the burst operation. Logic gate LG
54
supplies the result of the AND operation of read command signal READ and burst operation end signal /BSTEND as an output. Thus the output of logic gate LG
54
is set to an H level at the start of the reading operation and maintained at an H level until the end of the burst operation.
Therefore, when the read command is designated by the combination of command control signals supplied as inputs to logic gate LG
50
, read command signal READ is set to an H level by flip flop
515
at the rise of clock signal CLK.
After the reading operation is started, the output of logic gate LG
54
is turned to an L level in response to the end of the burst operation. Through taking in the L level output via logic gate LG
52
from LG
54
at the rising edge of clock signal CLK, flip flop
515
resets read command signal READ to an L level.
Logic gate LG
50
receives a row address strobe signal /RAS, a column address strobe signal /CAS, a chip select signal /CS and a write enable signal /WE. The combination of L level /CAS and /CS signals and H level /RAS and /WE signals designates the read command and causes the output of logic gate LG
50
to be set to an H level.
In response to the activation of read command signal READ supplied as an output from control signal generation circuit
510
, various internal control signals are activated to carry out the operation according to the read command. As an example, the generation of internal control signals for a column-related reading operation of the DRAM will be described below.
FIG. 15
is a circuit diagram showing a structure of a control signal generation circuit
520
supplying as an output a preamplifier activation signal PAE, which is one of internal control signals relating to the column-related reading operation.
With reference to
FIG. 15
, control signal generation circuit
520
includes a delay circuit
522
receiving clock signal CLK and supplying clock signal CLK delayed by a delay time td
0
as an output, a logic gate LG
60
supplying the result of an AND operation of read command signal READ and the output of delay circuit
522
, a delay circuit
524
delaying the output of logic gate LG
60
(by a delay time td
1
), a delay circuit
526
delaying the output of delay circuit
524
(by a delay time td
2
) and a logic gate LG
62
carrying out an AND operation of the outputs of delay circuits
524
and
526
. Logic gate LG
62
supplies preamplifier activation signal PAE as an output.
FIG. 16
is a circuit diagram showing a structure of a control signal generation circuit
530
generating a column decoder activation signal CDE, which is one of the control signals relating to the column-related reading operation like the preamplifier activation signal.
With reference to
FIG. 16
, control signal generation circuit
530
supplies column decoder activation signal CDE according to read command signal READ and clock signal CLK, similarly to control signal generation circuit
520
.
Though control signal generation circuit
530
has a similar structure to control signal generation circuit
520
, differences exist in that delay circuits
522
,
524
and
526
in control signal generation circuit
520
are replaced with delay circuits
532
,
534
and
536
for adding different delay times td
3
, td
4
and td
5
, respectively, in control signal generation circuit
530
, and that control signal generation circuit
530
includes an OR gate as a logic gate LG
66
for supplying control signal CDE as an output.
The activation and inactivation of internal control signals, including PAE and CDE are required to be carried out at appropriate timing for the correct reading operation. The timing is adjusted through the suitable setting of delay time added by a group of delay circuits to a reference control signal, which is obtained as the result of AND operation of read command signal READ and the signal obtained by delaying clock signal CLK.
FIG. 17
is a timing chart referenced for describing operations of control signal generation circuits
520
and
530
.
As shown in
FIG. 17
, when the read command is designated according to the combination of command control signals /RAS, /CAS, /CS and /WE, the read command is taken in at the time of the rise of clock signal CLK at time t
0
. At time td
1
, that is, tdR after time t
0
, read command signal READ is activated (to an H level) by control signal generation circuit
510
.
When the sum of delay time added by delay circuit
522
to clock signal CLK and delay time added by delay circuits
524
and
526
to the output of logic gate LG
60
, that is, td
0
+td
1
+td
2
, has passed after time t
0
, preamplifier activation signal PAE is activated (to an H level) at time t
3
. On the other hand, the fall of clock signal CLK is transmitted to logic gate LG
62
after the time delay td
0
+td
1
. Hence, provided that the activation period of clock signal CLK is Tw, preamplifier activation signal PAE is maintained at an active state (H level) for the duration of Tw−td
2
and then attains an inactive state (L level) at time t
4
.
Column decoder activation signal CDE is activated (to an H level) in response to the rise of clock signal CLK at time t
2
, that is, the sum of delay time added at delay circuits
532
and
534
, td
3
+td
4
, has elapsed after time t
0
.
The falling edge of clock signal CLK is transmitted to logic gate LG
66
via delay circuits
532
and
534
in a similar manner. As delay time td
5
is further added to one input to logic gate LG
66
by delay circuit
536
, column decoder activation signal CDE is maintained at an active state for the duration of Tw+td
5
and inactivated (to an L level) again at time t
5
.
Thereafter, while read command signal READ is in an active state, the activation and inactivation of these control signals are carried out at the timing as described above in response to the rising and falling edges of clock signal CLK.
In control signal generation circuits
510
and
520
, through the suitable setting of delay times td
0
~td
5
, c
Cunningham Terry D.
McDermott & Will & Emery
Nguyen Long
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