Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2001-10-31
2003-01-07
Phan, Trong (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S149000
Reexamination Certificate
active
06504741
ABSTRACT:
BACKGROUND OF THE INVENTION
A) Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device in which a storage electrode of a capacitor is connected to a gate electrode of a transistor.
B) Description of the Related Art
To implement a high-performance and high-speed information processing system, a content addressable memory (CAM) has attracted attention. In the CAM, a matching state between the memory contents stored in a memory cell and a signal supplied from an external device can be detected by a logical cell. The memory cell ordinarily includes a static random access memory (SRAM).
The inventor of the present invention has proposed a CAM including a dynamic random access memory (DRAM) in the memory cell. In the structure, even when a complementary signal is to be memorized, the basic unit of the memory cell includes two access transistors, two capacitors, and four search/compare transistors (for 3-valued CAM). However, a suitable driving technique and a suitable testing technique for the CAM have not been established yet.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device capable of efficiently drive a circuit in which a storage electrode of a capacitor is connected to a gate electrode of a transistor.
Another object of the present invention to provide a semiconductor device and an inspection method capable of inspecting with high precision a circuit in which a storage electrode of a capacitor is connected to an impurity diffusion region of a surface layer of a semiconductor substrate and a gate electrode of a transistor.
According to one aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; a plurality of cells regularly disposed on one surface of said semiconductor substrate, each said cell including a first transistor and a second transistor, each of said first and second transistors including a first current terminal, a second current terminal, and a gate terminal for controlling a conduction state between said first and second terminals, said second current terminal of said first transistor being connected to said gate terminal of said second transistor; a bit line connected to said first current terminals of said first transistors of part of said cells; a word line connected to said gate terminals of said first transistors of part of said cells; a first wiring connected to a point in a circuit connected to said first current terminal of said second transistor of part of said cells; a second wiring connected to a point of a circuit connected to said second current terminal of said second transistor of each of cells selected from said cells; a bit line driver for setting said bit line to either one of a first voltage state and a second voltage state with a voltage higher than a voltage of the first voltage state; a first voltage generator circuit for generating a third voltage on said first wiring, said third voltage being higher than said first voltage and lower than said second voltage; a second voltage generator circuit for generating a fourth voltage on said second wiring, said fourth voltage being higher than said third voltage and equal to or lower than said second voltage; and a voltage detector circuit for detecting a voltage appearing on said second wiring.
With the bit line set to the first voltage, when the first transistor is turned on, the gate electrode of the second transistor is charged up to almost the first voltage. When the bit line is set to the second voltage state, the gate electrode of the second transistor is charged up to almost the second voltage. The third and fourth voltages are applied respectively via the first wiring and the second wiring respectively to the first and second current terminals of the second transistor. When the gate electrode of the second transistor is in the second voltage state, since the third voltage is higher than the first voltage, the gate leakage current can be lowered when compared with a case in which the first voltage is applied via the first wiring to the first current terminal of the second transistor. This enhances the retention characteristic of charge stored in the gate electrode.
According to one aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; a first transistor formed on a surface of said semiconductor substrate, said first transistor including a first gate electrode, a first impurity diffusion region, and a second impurity diffusion region; said first and second impurity diffusion regions being formed in a surface layer of said semiconductor substrate respectively on both sides of said first gate electrode; a signal line for selectively applying either one of a first voltage and a second voltage to said first impurity diffusion region; a control line for applying a control signal to the first gate electrode of said first transistor, said control signal controlling a conduction state of said first transistor; a second transistor formed on a surface of said semiconductor substrate, said second transistor including a second gate electrode connected to said second impurity diffusion region, a third impurity diffusion region, and a fourth impurity diffusion region; said third and fourth impurity diffusion regions being formed in a surface layer of said semiconductor substrate respectively on both sides of said second gate electrode; and a voltage generator circuit for generating, in an ordinary operation, a third voltage on said third impurity diffusion region and for applying, in an inspection, a fourth voltage to said third impurity diffusion region; each of said third and fourth voltages being between said first voltage and said second voltage; a voltage difference between said first and fourth voltages and a voltage difference between said second and fourth voltages are each larger than a smaller one of a voltage difference between said third voltage and said first voltage and a voltage difference between said third voltage and said second voltage.
When the circuit is set to the voltage applied state in the inspection, the gate leakage current of the second transistor can be reduced. The magnitude of the junction leakage current flowing from the second gate electrode via the second impurity diffusion region to the substrate can be easily inspected.
According to one aspect of the present invention, there is provided a transistor inspection method of inspecting a semiconductor device, said semiconductor device comprising: a first transistor formed on a surface of a semiconductor substrate, said first transistor including a first gate electrode, a first impurity diffusion region, and a second impurity diffusion region; said first and second impurity diffusion regions being formed in a surface layer of said semiconductor substrate respectively on both sides of said first gate electrode; and a second transistor formed on a surface of said semiconductor substrate, said second transistor including a second gate electrode connected to said second impurity diffusion region, a third impurity diffusion region, and a fourth impurity diffusion region; said third and fourth impurity diffusion regions being formed in a surface layer of said semiconductor substrate respectively on both sides of said second gate electrode, wherein data are stored by storing charge via said first transistor to a gate electrode of said second transistor to set a voltage of said gate electrode of said second transistor to a first voltage or a second voltage, said semiconductor inspection method comprising the steps of: applying a voltage between said first voltage and said second voltage to said third impurity diffusion region of said second transistor and setting said fourth impurity diffusion region to a floating state; storing charge to said gate electrode of said second transistor via said first transistor to set said gate electrode to said first voltage; and inspecting a retention characte
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Phan Trong
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