Patent
1991-12-06
1992-08-18
Wojciechowicz, Edward J.
357 15, 357 68, H01L 2980
Patent
active
051403870
ABSTRACT:
An aligned metal gate is formed on a semiconductor substrate surface between a source region and a drain region of the substrate. Precise alignment of the boundaries of the gate with the boundaries of the source and drain regions is obtained by shadowing a photoresist coating over metal deposited onto the substrate surface, while photochemically dissociating the photoresist over metal deposited onto an oxide layer formed over the source and drain regions of the substrate. The developed photoresist is removed, and the undeveloped photoresist is hard-baked to serve as a protective coating for the metal between the source and drain regions. The metal over the source and drain regions is etched away, leaving the metal between the source and drain regions to function as an electronic gate.
REFERENCES:
patent: 3503124 (1970-03-01), Wanlass et al.
patent: 3609477 (1977-09-01), Drangeid et al.
patent: 4266333 (1981-05-01), Reichert
patent: 4546540 (1985-10-01), Ueyanagi et al.
patent: 4566021 (1986-01-01), Yokoyama
patent: 4603472 (1986-08-01), Schwabe etal.
patent: 4951111 (1990-08-01), Yamamoto
Ning, T. H. et al, "Self-Aligned Silicon MESFET or JFET" IBM Tech. Disc. Bull. vol. 22, No. 7, Dec. 1979, p. 2918.
Okazaki Eldon
Petersen Howard L.
Crane Sara W.
Lockheed Missiles & Space Company Inc.
Morrissey John J.
Wojciechowicz Edward J.
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