Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-06-05
2002-11-26
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S684000, C345S211000
Reexamination Certificate
active
06486865
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device used for efficiently changing the position of display data displayed on a display device, an image display system using the semiconductor device, and an electronic system using the image display system. More particularly, the present invention relates to the sequence of supplying display data, which is stored in a display RAM (Random Access Memory), to an image display system.
2. Related Art
For displaying data on a liquid crystal display (hereinafter referred to as an “LCD”) which serves as a display device, a semiconductor device called an LCD driver is employed. There are two types of LCD drivers, i.e., a segment driver (hereinafter referred to as an “X driver”) for driving data electrodes of the LCD, and a common driver (hereinafter referred to as a “Y driver”) for driving scanning electrodes of the LCD. The X driver is a circuit for receiving display data to be displayed on the LCD from a display RAM through a circuit called a display controller, and converting the received data into a voltage required for driving the LCD. The Y driver is a circuit for receiving, through the display controller, data to select a line in which a data signal supplied from the X driver is to be written, and converting a voltage for selection
on-selection into the voltage required for driving the LCD. Usually, the selected line is scanned by a line-at-a-time scheme.
With advances in the semiconductor manufacturing technology and the circuit technology, it has recently become possible to integrate an X driver, a display RAM and a display controller into one IC, or further integrate a Y driver and a display power supply circuit for an LCD as well. As a result, a reduction in the number of chips used in a display system and a reduction in power consumed by the display system are promoted.
FIG. 2
is a schematic block diagram of a conventional image display system.
The conventional image display system includes a microprocessor (hereinafter referred to as an “MPU”)
1
. The MPU
1
is constituted by a central processing unit, and has the function of generating a signal to write display data, which is to be displayed on an LCD, in a display RAM. An oscillator
2
has the function of generating a reference clock required for displaying data on the LCD. A RAM built-in X driver
3
is a one-chip unit incorporating a display RAM
31
, a display controller which is, though not denoted in
FIG. 2
, made up of an MPU logic
33
and a display logic
34
, and an X driver
32
. A Y driver
4
is a circuit for receiving, through the display controller, data to select a line in which a data signal supplied from the X driver
32
is to be written, and converting a voltage for selection
on-selection into a voltage required for driving the LCD. A display power supply
5
has the function of generating a voltage required for displaying data on the LCD. LCD panels
61
,
62
are each the same panel, but represent the cases displaying different screen images. The display RAM
31
is constituted by a dual port RAM that interfaces with the MPU and the display system in asynchronous relation. The X driver
32
is a circuit for converting the display data read out of the display RAM
31
into a voltage required for displaying data on the LCD. The MPU logic circuit
33
has the function of performing processing related to the MPU
1
such as processing of commands sent from the MPU
1
and control of the display data to be read out of and written in the display RAM
31
. The display logic circuit
34
has the function of performing control related to display such as control of the operation of reading the display data out of the display RAM
31
and supplying the read-out data to the X driver
32
and control of the Y driver
4
. A memory area
301
serves as an area for storing the display data. An MPU read/write circuit
302
is a circuit for performing control of reading/writing made on the memory area
301
. An MPU row address
303
is a decoder for indicating an address of the memory area
301
in the Y (row) direction in the reading/writing mode of the MPU. An MPU column address
304
is a decoder for outputting an address of the memory area
301
in the X (column) direction in the reading/writing mode of the MPU. A display address
305
is a decoder for reading the display data, which is to be supplied to the X driver
32
, from among the display data stored in the memory area
301
.
The LCD panel
61
has a display capacity of 320×240 dots; namely, it has 240 lines of common electrodes on the left side of the panel and 320 lines of segment electrodes on the upper side thereof. The display RAM
31
incorporated in the RAM built-in X driver
3
has the same display capacity as the LCD panel
61
, i.e., 320×240 bits. The MPU column address
304
of the display RAM
31
includes 320 addresses corresponding to the number of dots in the X direction of the LCD panel
61
. Because of 8-bit simultaneous writing, the MPU row address
303
of the display RAM
31
includes 30 addresses corresponding to a result of dividing
240
, i.e., the number of dots in the Y direction of the LCD panel
61
, by 8. The MPU
1
can write data, which is to be displayed, at any desired position in the display RAM
31
through the MPU logic circuit
33
and the MPU read/write circuit
302
by designating any desired addresses to the MPU column address
304
and the MPU row address
363
through the MPU logic circuit
33
. One bit of the display data corresponds to one dot for display in the LCD panel
61
. If the display data is “0”, the predetermined dot in the LCD panel
61
corresponding to that display data is displayed white, and if the display data is “1”, it is displayed black.
The display address
305
includes 240 addresses corresponding to the number of dots in the Y direction of the LCD panel
61
. The display logic circuit
34
designates any one of the display addresses “0”-“239”. When the display address is designated, the display RAM
31
outputs data of 320 bits corresponding to the number of dots in the X direction of the LCD panel
61
, and supplies the data to the X driver
32
. The X driver
32
converts the received display data into a voltage required for driving the LCD panel
61
, and supplies the voltage to the LCD panel
61
for driving the same.
FIG. 3
is a time chart of signals at respective points for explaining the operation of the image display system of FIG.
2
. In
FIG. 3
, the vertical axis represents a logical level and the horizontal axis represents time. The operation of
FIG. 2
will be described below with reference to FIG.
3
.
A signal
401
is a reset (RES) signal. A signal
402
is a reference clock DCLK supplied from the oscillator
2
. Signals
403
,
412
are each an output of a not-shown address counter included in the display logic circuit
34
. Signals
404
,
413
are each X driver data given by the data in the display RAM
31
that is taken in by the X driver
32
at a fall of the reference clock DCLK. A signal
405
is a selection signal YDATA supplied to the Y driver
4
. Signals
406
-
411
are selected data transferred by a 240-step shift register (not shown) in the Y driver
4
.
As indicated by the signal
403
, the output of the not-shown address counter included in the display logic circuit
34
is initialized to “0” with the rise edge of the reset signal RES. After that, the output of the not-shown address counter is counted up with the rise edge of the reference clock DCLK
402
, and is returned to “0” upon the count reaching “239” as indicated by the signal
403
. The signal
403
, which is an output signal of the address counter, is supplied to the display address
305
, whereby the display address is designated from “0” to “239” in sequence.
The YDATA
405
is a selection-signal supplied to the Y driver
4
. “H” of the YDATA
405
corresponds to line selection and “L” corresponds to non-selection. The YDATA
405
turns to “H” from the rise edge of the rese
Hogan & Hartson LLP
Seiko Epson Corporation
Wu Xiao
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