Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2002-04-24
2004-08-24
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S643000
Reexamination Certificate
active
06781216
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device, which has at least one dummy pattern to protect wiring patterns from corrosion.
2. Description of the Related Art
A semiconductor device having a metalized wiring pattern in the related art is formed by the process described below with reference to
FIGS. 8A through 8C
.
Referring to
FIG. 8A
, a semiconductor substrate
101
having circuit elements, such as transistors, in a circuit area of a chip area on its surface is prepared, and then, a metal layer which is formed of Aluminum are formed on the entire main-surface of the semiconductor substrate
101
. Then, metalized wiring patterns
102
are formed by etching the metal layer to make an interconnection of the circuit elements.
Next, referring to
FIG. 8B
, a first insulating layer
103
, such as a silicon oxide layer, is formed on the entire main-surface of the semiconductor substrate
101
and on the exposed surface of the metalized wiring patterns
102
by the CVD process. After that, a SOG (Spin On Grass) layer
104
as a second insulating layer is coated on the first insulating layer
103
to planarized its surface. According to the spin coating process, the thick SOG layer is formed in an area where no wiring patterns is formed, and the thin SOG layer is formed on the wiring patterns. Then, a third insulating layer
105
, such as a silicon oxide layer, is formed on the SOG layer by the CVD process.
After that, referring to
FIG. 8C
, the first insulating layer
103
, the SOG layer
104
, the third insulating
105
layer only in an grid line area is removed to make an opening
106
until the surface of the semiconductor is exposed. This process is very important to avoid cracking the semiconductor device at the scribing process.
However, as the SOG layer is exposed at an edge
1000
of the opening
106
, moisture comes into the semiconductor device because the SOG layer has hygroscopicity. As a result, the metalized wiring patterns are corroded.
SUMMARY OF THE INVENTION
An objective of the invention is to resolve the above-described problem and to provide a semiconductor device having a dummy pattern to protect wiring patterns formed in the semiconductor device from corrosion.
The objective is achieved by a semiconductor device including a semiconductor substrate having a grid-line area and a chip area, the chip area having a circuit area and a dummy area surrounding the circuit area, circuit patterns formed on the substrate in the circuit area, a first dummy pattern which is formed of the same material as the circuit pattern, formed in the dummy area, the dummy pattern encompassing the circuit area, a first insulating layer formed on an entire surface of the semiconductor substrate, a second insulating layer formed only on the first insulating layer which is formed on the semiconductor substrate and on the circuit patterns; and a third insulating layer formed on the exposed first insulating layer and the second insulating layer.
The objective is further achieved by a method for manufacturing a semiconductor device including a step for preparing a semiconductor substrate having a grid-line area and a chip area, the chip area having a circuit area and a dummy area surrounding the circuit area, a step for forming a conductivity layer on the semiconductor substrate, a step for forming circuit patterns in the circuit area and a dummy pattern encompassing the circuit area in the dummy area by etching the conductivity layer, a step for forming a first insulating layer formed on an entire surface of the semiconductor substrate, a step for forming a second insulating layer on the first insulating layer, a step for removing the second insulating layer which is formed on the first insulating layer on the dummy pattern until the surface of the first insulating layer is exposed, a step for forming a third insulating layer formed on the exposed first insulating layer and on the second insulating layer; and, a step for removing the first, second and third insulating layers in the grid-line area.
REFERENCES:
patent: 5798298 (1998-08-01), Yang et al.
patent: 5808363 (1998-09-01), Watanabe
patent: 6261883 (2001-07-01), Koubuchi et al.
patent: 56-107570 (1981-08-01), None
patent: 07-161706 (1995-06-01), None
patent: 08-181208 (1996-12-01), None
patent: 09139431 (1997-05-01), None
patent: 09-139431 (1997-05-01), None
patent: 10178011 (1998-06-01), None
patent: 10-270445 (1998-10-01), None
Duy Mai Anh
Fahmy Wael
Mimura Junichi
Oki Electric Industry Co. Ltd.
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