Semiconductor device having wafer level chip scale packaging...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C257SE23021, C257SE21536, C438S393000, C438S613000

Reexamination Certificate

active

07919860

ABSTRACT:
One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.

REFERENCES:
patent: 6198136 (2001-03-01), Voldman et al.
patent: 7005747 (2006-02-01), Koizumi
patent: 2004/0183209 (2004-09-01), Lin
patent: 2005/0146838 (2005-07-01), Shioga et al.
patent: 2007/0111462 (2007-05-01), Lee et al.
patent: 2007/0145527 (2007-06-01), Yamabi et al.
patent: 2000307403 (2000-11-01), None
patent: 2002016222 (2002-01-01), None

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