Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
1999-10-19
2001-09-25
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S206000, C257S350000, C257S390000, C257S622000, C257S397000, C257S369000
Reexamination Certificate
active
06294803
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a structure of a semiconductor device and method of fabricating the same. Although the present invention is suitable for a wide range of applications, it is particularly suitable for a highly integrated transistor.
2. Discussion of the Related Art
A conventional structure of a semiconductor device and method of fabricating the same will be explained with reference to the attached drawings.
FIG. 1
is a cross-sectional view of a conventional structure of a semiconductor device. A field oxide layer
15
is formed at a field region of a semiconductor substrate
11
defined as an active region and a field region. A gate insulating layer
16
is formed on a predetermined portion of the active region and a gate electrode
19
is formed on the gate insulating layer
16
. Sidewall spacers
21
are formed on both sides of the gate insulating layer
16
and the gate electrode
19
, and a source/drain impurity diffusion region
22
having a LDD (lightly doped drain) structure is formed in the substrate
11
on each side of the gate electrode
19
adjacent to the sidewall spacers
21
.
FIGS. 2A-2E
are cross-sectional views showing a conventional method of fabricating a semiconductor device having the aforementioned structure. First, an initial oxide layer
12
is formed in order to release stress imposed on an interface of a semiconductor substrate and a nitride layer
13
is deposited on the entire surface of the initial oxide layer
12
, as shown in FIG.
2
A.
Subsequently, a first photo resist layer
14
, as shown in
FIG. 2B
, is coated on the nitride layer
13
and then is patterned by an exposure and development process. Using the patterned first photo resist layer
14
as a mask, the nitride layer
13
is partially removed to define a field region and an active region. A region where the nitride layer
13
has been removed is defined as a field region, whereas a region below the remaining nitride layer
13
is defined as an active region. Using the first photo resist layer
14
as a mask, ions are implanted into the field region to increase the insulation characteristic of the field region. In this process, by increasing the concentration of the implanted ions, the value of the threshold voltage can be increased.
Referring to
FIG. 2C
, the first photo resist layer
14
used as a mask for ion implantation is removed. Using the nitride layer
13
as a mask, an oxidation process is carried out to form a field oxide layer
15
in the field region. The nitride layer
13
and the initial oxide layer
12
are removed. A gate insulating layer
16
is formed on the surface of the substrate
11
between the field oxide layers
15
and then a polysilicon layer
17
for a gate electrode is formed on the entire surface of the gate insulating layer
16
. Thereafter, a second photo resist layer
18
is provided on the polysilicon layer
17
and patterned by an exposure and development process.
Referring to
FIG. 2D
, using the second photo resist layer
18
as a mask, the polysilicon layer
17
and the gate insulating layer
16
are partially removed so that a gate electrode
19
is formed. Using the gate electrode
19
as a mask, impurity ions are lightly implanted into the entire surface of the substrate
11
to form a lightly doped impurity regions
20
in the substrate
11
.
Finally, as shown in
FIG. 2E
, an insulating layer (not shown) is deposited on the entire surface including the gate electrode
19
and is subjected to etch back to form sidewall spacers
21
on both sides of the gate insulating layer
16
and the gate electrode
19
. After forming the sidewall spacers
21
, impurity ions are heavily implanted into the substrate
11
using the gate electrode
19
and the sidewall spacers
21
as masks to form a source/drain impurity region
22
having a LDD structure.
Nevertheless, a conventional structure of a semiconductor device and method of fabricating the same has the following problems.
Since a field oxide layer used as an isolation region for isolating devices occupies a large area, it is not feasible for fabricating highly integrated devices.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a structure of a semiconductor device that is suitable for a highly integrated transistor and a method of fabricating the same that substantially obviate one or more of problems due to limitations and disadvantages of the related art.
An object of the invention is a semiconductor device in which a field oxide layer is formed vertically to occupy a minimal area and a method of fabricating the same.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the semiconductor device includes a semiconductor substrate, a plurality of active regions of concave type and convex type formed alternatively on a semiconductor substrate, and field insulating layers some of which are formed to be parallel with the semiconductor substrate and the other of which are formed to be perpendicular to the semiconductor substrate in active regions and field regions.
In another aspect of the invention, the method of fabricating the semiconductor device includes the steps of providing a semiconductor substrate, forming a plurality of active regions of concave type and convex type formed alternatively on the semiconductor substrate, and forming field insulating layers some of which are formed to be parallel with the semiconductor substrate and the other of which are formed to be perpendicular to the semiconductor substrate in field regions and active regions.
In another aspect of the invention, the semiconductor device including a substrate, a plurality of active regions formed in rows and columns in the substrate, one active region of each adjacent pair of active regions in a row being formed in a trench in the substrate, the trench including first and second walls extending in a direction perpendicular to the row, and a field insulating layer on each of the first and second walls.
In another aspect of the invention, the semiconductor device includes a substrate, a plurality of active regions formed in rows and columns in the substrate, each of the active regions in a row being at a vertical level in the substrate different from the vertical level of an adjacent active region in a row, and a field insulating layer separating adjacent active regions in a row, each of the field insulating layers having a thickness in the direction of a row and a height in a direction perpendicular to the substrate and to the thickness of the layer, the height of each of the field insulating layer being greater than the thickness thereof.
In another aspect of the invention, the method of fabricating a semiconductor device having a substrate, the device includes the steps of forming a plurality of active regions on the substrate, the active regions having recessed and elevated types and being alternatively in parallel with the substrate, respectively, and forming a plurality of first and second field insulating layers at field regions adjacent to the active regions.
In a further aspect of the invention, the method of fabricating a semiconductor device having a substrate comprising the steps of forming a first photo resist layer on the substrate, patterning the first photo resist layer to expose a portion of the substrate, forming a trench in the substrate using the patterned photo resist as a mask, removing the photo resist layer, forming a first insulating layer on the substrate including the trench,
LG Semicon Co. Ltd.
Loke Steven
Morgan & Lewis & Bockius, LLP
Owens Douglas W.
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