Semiconductor device having timing stabilization circuit...

Details Semiconductor device having timing stabilization circuit... Semiconductor device having timing stabilization circuit...

1998-07-02

2002-12-31

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000, C375S376000

Reexamination Certificate

active

06501309

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device equipped with a timing-stabilization circuit such as a DLL (delay-locked loop) circuit.
2. Description of the Related Art
FIG. 1
is a block diagram of a configuration in which a DLL circuit is used as a timing-stabilization circuit for data-input operations.
The configuration of
FIG. 1
includes an input buffer
501
, a variable-delay circuit
502
, a clock-control circuit
503
, an input circuit
504
, a frequency divider
505
, a phase comparator
506
, a delay-control circuit
507
, a variable-delay circuit
508
, a dummy-input circuit
509
, a dummy-input buffer
510
, and a lock-on detector
511
.
A clock signal CLK input to the input buffer
501
is compared with a reference-voltage level Vref, and is output as an internal-clock signal i-clk from the input buffer
501
. The internal-clock signal i-clk is delayed by the variable-delay circuit
502
by an appropriate delay amount, and is supplied to the input circuit
504
via the clock-control circuit
503
. The input circuit
504
uses the internal-clock signal i-clk as a synchronization signal to latch input data. The latched input data is then supplied from the input circuit
504
to internal circuits of the semiconductor device.
The signal path from the input of the clock signal CLK to the input circuit
504
inevitably introduces a delay which is inherent to the circuit, so that the input data supplied from the input circuit
504
to the internal circuits has a timing displacement relative to the input clock signal CLK. In order to ensure that the input data supplied to the internal circuits is adjusted to have a predetermined timing relation with the clock signal CLK supplied from an external source, a DLL circuit mainly comprised of the phase comparator
506
, the delay-control circuit
507
, and the variable-delay circuit
508
is employed.
The internal-clock signal i-clk is subjected to frequency division in the frequency divider
505
to generate a dummy-clock signal d-clk and a reference-clock signal c-clk. The dummy-clock signal d-clk is supplied to the variable-delay circuit
508
. The variable-delay circuit
508
is controlled to delay the dummy-clock signal d-clk by the same delay amount as that applied by the variable-delay circuit
502
. The dummy-clock signal d-clk delayed by the variable-delay circuit
508
is then supplied to the phase comparator
506
via the dummy-input circuit
509
and the dummy-input buffer
510
. Here, the dummy-input circuit
509
has the same delay characteristics as the input circuit
504
, and the dummy-input buffer
510
has the same delay characteristics as the input buffer
501
.
The phase comparator
506
makes a comparison of the reference-clock signal c-clk with the clock signal supplied from the dummy-input buffer
510
. To ensure that both clock signals have the same phase, the phase comparator
506
controls the delay amount of the variable-delay circuit
508
via the delay-control circuit
507
. In this manner, the clock signal supplied from the dummy-input circuit
509
is adjusted so as to have a predetermined timing relation with the input clock signal CLK.
When the clock-control circuit
503
is ignored, a total delay of the input buffer
501
, the variable-delay circuit
502
, and the input circuit
504
is equal to a total delay of the dummy-input buffer
510
, the variable-delay circuit
508
, and the dummy-input circuit
509
. Because of this, the input data supplied from the input circuit
504
ends up having the predetermined timing relation with the input clock signal CLK.
In this configuration, even when the characteristics of the input buffer
501
, the variable-delay circuit
502
, and the input circuit
504
are changed due to variations in a power voltage and/or temperature, the characteristics of the dummy-input buffer
510
, the variable-delay circuit
508
, and the dummy-input circuit
509
also change in the same manner. Because of this, the input data supplied from the input circuit
504
to the internal circuits always keeps the same timing relation with the input clock signal CLK regardless of a power-voltage variation and/or a temperature variation.
The lock-on detector
511
checks whether the DLL circuits has locked on, based on signals supplied from the phase comparator
506
. That is, the lock-on detector
511
checks whether the two clock signals subjected to phase comparison by the phase comparator
506
have the same phase. When a lock-on condition is established, the lock-on detector
511
controls the frequency divider
505
to lower the frequency of the dummy-clock signal d-clk and the reference-clock signal c-clk, thereby reducing power consumption.
The delay-control circuit
507
, when set to a maximum delay amount, outputs an overflow signal. Each of the variable-delay circuits
502
and
508
is comprised of a predetermined number of delay elements arranged in series, and is controlled by the delay-control circuit
507
. Because of this configuration, the number of usable delay elements is limited in nature. If the delay amount is set to a possible maximum amount, the variable-delay circuits
502
and
508
cannot further increase the delay. In this case, the overflow signal indicating detection of overflow is supplied to the clock-control circuit
503
. When overflow is detected, the clock-control circuit
503
selects the internal-clock signal i-clk bypassing the variable-delay circuit
502
rather than selecting the clock signal supplied from the variable-delay circuit
502
, and supplies the internal-clock signal i-clk to the input circuit
504
.
Clock stabilization using the DLL circuit as described above is employed with respect to not only an input portion of the semiconductor device but also an output portion thereof. In such a case, data-output operations can be conducted at predetermined stable timings.
The configuration of
FIG. 1
has a drawback in that overflow cannot be detected outside the semiconductor device. During a test of the semiconductor device, therefore, it is impossible to know whether data is input by using the internal-clock signal i-clk delayed by the variable-delay circuit
502
or by using the internal-clock signal i-clk bypassing the variable-delay circuit
502
. This prevents an appropriate test from being carried out in an attempt to learn characteristics of the semiconductor device.
Further, the configuration of
FIG. 1
does not take into consideration how to detect overflow when the variable-delay circuits are comprised of a rough-delay circuit and a fine-delay circuit arranged in series or when a plurality of internal clocks are used in the semiconductor device.
Moreover, the configuration of
FIG. 1
continues to supply the internal-clock signal i-clk to the variable-delay circuit
502
and to supply the dummy-clock signal d-clk to the variable-delay circuit
508
even after overflow is detected. As previously described, upon detection of overflow, the internal-clock signal i-clk which bypasses the variable-delay circuit
502
will be used as a synchronization signal for the data input. In this case, the delay control by the variable-delay circuit
502
is irrelevant to the operations of the semiconductor device. There is no need, therefore, to supply the internal-clock signal i-clk to the variable-delay circuit
502
. Also, there is no need to supply the dummy-clock signal d-clk to the variable-delay circuit
508
such that control of the dummy-clock signal d-clk is carried out at relatively short intervals by the variable-delay circuit
508
. Sustained supply of the internal-clock signal i-clk to the variable-delay circuit
502
and of the dummy-clock signal d-clk having a relatively high frequency to the variable-delay circuit
508
results in excessive power consumption.
Accordingly, there is a need for a semiconductor device which allows overflow of a variable-delay circuit in a DLL circuit to be detected outside t

Affiliated with

Also associated with

Rating

Semiconductor device having timing stabilization circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having timing stabilization circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having timing stabilization circuit... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2947213