Semiconductor device having thin film transistor with diffusion

Details Semiconductor device having thin film transistor with diffusion Semiconductor device having thin film transistor with diffusion

1995-06-13

1996-07-16

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257 67, 257 72, 257 74, 257351, 257354, H01L 2976, H01L 2904, H01L 2701

Patent

active

055369510

ABSTRACT:
A p-well region is formed in a main surface of a semiconductor substrate. A contact electrode is electrically connected to a predetermined n-type impurity region formed in a surface of the p-well region. A diffusion preventing layer is formed between the contact electrode and a drain region of a TFT. An interconnection layer is formed on the semiconductor substrate with an interlayer insulating film therebetween. A diffusion preventing layer is also formed between the interconnection layer and a source region of the TFT. Diffusion preventing layers are further formed between a channel region of the TFT and the source/drain regions of the TFT.

REFERENCES:
patent: 4772927 (1988-09-01), Saito et al.
patent: 5060036 (1991-10-01), Choi
patent: 5308998 (1994-05-01), Yamazaki et al.
patent: 5327001 (1994-07-01), Wakai et al.
patent: 5349206 (1994-09-01), Kimura
"Stacked CMOS SRAM Cell", C. E. Chen et al., IEEE Electron Device Letters, vol. EDL-4, No. 8, Aug. 1983, pp. 272-274.
A High Density SRAM Cell Using Poly-Si PMOS FET, T. Yamanaka et al., Electronic Information Communication Institute, Technology Research Report, vol. 89, No. 67, 1989, pp. 1-6.

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