Semiconductor device having test mark

Details Semiconductor device having test mark Semiconductor device having test mark

2000-07-20

2004-06-01

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

Reexamination Certificate

active

06744143

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a test mark and, more particularly, to a semiconductor device in which an extension of a crack from the test mark is prevented.
2. Description of the Related Art
Referring to
FIG. 13A
, a semiconductor wafer
10
contains a plurality of block portions
11
. In the process of fabricating semiconductor elements on the semiconductor wafer
10
, each of the block portions
11
is exposed to light in one shot process.
Referring to
FIG. 13B
, which shows an enlarged block portion
11
, a plurality of semiconductor chips
12
are fabricated in the block portion
11
, and also dicing lines or tracks
13
along which the block portion
11
will be diced and separated into semiconductor chips
12
are formed between the semiconductor chips
12
. Generally, a test mark (not shown) is formed in the dicing line
13
, for example, for measuring a thickness of a deposited layer, determining overlay accuracy, or measuring a characteristic of a device.
Referring next to
FIG. 14A
, there is shown an enlarged plan view of a test mark fabricated in the dicing line. Also, a cross sectional view along lines B—B in
FIG. 14A
is shown in FIG.
14
B. As shown, a semiconductor substrate
21
bears a first insulating layer
22
made of tetraethyl orthosilicate including boron and phosphorus which has good characteristic of step coverage, referred to “BPTEOS layer” hereinafter, which in turn supports a second insulating layer
23
made of tetraethyl orthosilicate, referred to “TEOS layer” hereinafter. A recess or concave
24
for use as a test mark is formed in the TEOS and BPTEOS layers,
22
and
23
, and terminated at the surface of the substrate
21
facing to the BPTEOS layer
22
. When viewed from above, i.e., from the direction indicated by the arrow
29
in
FIG. 14B
, the recess
24
has a square in configuration defined by four vertical walls, and one side of the square recess
24
is about 10 to 100 &mgr;m in length.
Disadvantageously, the BPTEOS layer
22
is melted or deformed in a heat treatment such as a sintering step, on the other hand, the TEOS layer
23
is scarcely deformed in the step. This results in that cracks
27
are formed in the BPTEOS layer
22
at the corner of the recess
24
near the TEOS layer
23
as shown in FIG.
14
A. The cracks
27
extend outwardly and then destroy the semiconductor elements or another test marks (not shown) fabricated on the semiconductor substrate
21
.
Particularly, the test mark has a large area in horizontal cross section such as a square configuration of 10 &mgr;m×100 &mgr;m or a rectangular configuration of 1 &mgr;m×100 &mgr;m, for example, and has four corners. Therefore, stresses concentrate at these corners by the deformation of the BPTEOS layer
22
, causing the formation of the cracks
27
.
In order to prevent formation of the cracks
27
, a structure shown in
FIGS. 15A and 15B
has been proposed. In the structure, a metal layer
25
such as a capacitor lower electrode is formed on the BPTEOS
22
as a stop layer, thereby a recess
24
is formed only in the TEOS layer
23
above the metal layer
25
.
However, for example, the thickness of the TEOS layer
23
can not be measured exactly by the use of the test mark. This is because the metal layer
25
is formed in the TEOS layer
23
. Therefore, the test mark is prohibited from being used for the measurement of the thickness of the TEOS layer
23
. Also, the presence of the metal layer
25
prevents the exact determination of overlay accuracy. Therefore, the mark is not used for determining overlay accuracy.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor device having a test mark which prevents extension of a crack arisen at the corner of a recess which is used as a test mark, thereby adverse affect to a semiconductor element by the crack is prevented.
To this end, the inventors of the present invention have made intensive research on this subject. As a result, the inventors have found that by forming a metal layer on the BPTEOS layer near the corners of the recess, thereby the extension of the cracks formed in the BPTEOS layer can be terminated by the metal layer.
That is, present invention provides a semiconductor device having a test mark. The device comprises a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at high or an elevated temperature; a recess formed in the first and second TEOS layers and terminated at the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.
In the case that a crack is arisen in the first TEOS layer at the corner of recess by the deformation of the first TEOS layer, the extension of the crack can be terminated by the metal layer. Thereby, the destruction of a semiconductor element or another test mark, which is caused by the extension of the crack, can be prevented.
The first TEOS layer may contain boron and/or phosphorus. Such a TEOS layer containing boron and/or phosphorus, which is referred as a BPTEOS layer, is easy to melt or deform, so that a crack is easy to arise.
Preferably, the metal layer is a square-shaped layer surrounding the recess. By use of such a metal layer, the extension of a crack can be terminated.
The metal layer may be an L-shaped layer surrounding the corner of the recess. This is because that most of the cracks are arisen at the corner of the recess and extend in a diagonal direction of the recess.
The metal layer may be a delta-shaped layer of which one side opposes to the corner of the recess. The extension of a crack can be terminated effectively by such a metal layer.
Also, a semiconductor device of the present invention may further comprise an outer metal layer formed outside of the metal layer so that the outer metal layer opposes to the corner of the recess through the metal layer.
A crack that extends through and outward the metal layer can be terminated by the outer metal layer.
Also, a semiconductor device of the present invention may further comprise a lower metal layer embedded in the first TEOS layer which extends between the top and bottom surfaces each neighboring to the semiconductor substrate and the metal layer. The extension of a crack can be terminated effectively by such an embedded metal layer.
The lower metal layer may consist of a plurality of cylindrical metal layers.
As can be seen from above description, a crack extended from the corner of the recess for use as a test mark can be terminated by the metal layer which is formed around the recess. Thereby, a production yield of a semiconductor device having such a test mark can be increased.


REFERENCES:
patent: 6093640 (2000-07-01), Hsu et al.
patent: 6118185 (2000-09-01), Chen et al.
patent: 10-189417 (1998-07-01), None
patent: 11-31645 (1999-02-01), None

Affiliated with

Also associated with

Rating

Semiconductor device having test mark does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having test mark, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having test mark will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3304732