Semiconductor device having test circuit

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371 2231, G01R 3128

Patent

active

058945482

ABSTRACT:
Test data is set in the flip-flop of a test circuit via a scan path in the test mode. A timing converting section forms a plurality of update signals of different timings in the test mode. A multiplexer formed in the test circuit selects one update signal from the plurality of update signals according to a timing converting signal stored in a register. The test data set in the flip-flop is supplied to the internal circuit at a timing defined by the selected update signal. That is, the update signal and timing converting signal are used to control the input timing of test data supplied to the internal circuit for each test circuit.

REFERENCES:
patent: 4879718 (1989-11-01), Sanner
patent: 5127008 (1992-06-01), Bassett et al.
patent: 5329188 (1994-07-01), Sikkink et al.
patent: 5389843 (1995-02-01), McKinney
patent: 5467354 (1995-11-01), Yamauchi
patent: 5526365 (1996-06-01), Whetsel

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