Semiconductor device having T-shaped gate structure...

Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means

Reexamination Certificate

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C438S574000

Reexamination Certificate

active

07148145

ABSTRACT:
Polysilicon lines are formed, featuring an upper portion extending beyond the lower portion that defines the required CD. Accordingly, metal silicide layers of increased dimensions can be formed on the upper portion of the polysilicon lines so that the resulting gate structures exhibit a very low final sheet resistance. Moreover, in situ sidewall spacers are realized during the process for forming the polysilicon lines and without additional steps and/or costs.

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patent: 6284613 (2001-09-01), Subrahmanyam
patent: 6395606 (2002-05-01), Huster et al.
patent: 6593618 (2003-07-01), Kamata et al.
patent: 0 991 113 (2000-04-01), None
Wolf et al., Silicon Processing for the VLSI Era, 1986, Lattice Press, vol. 1, pp. 124, 175, 182-183, 384-386, 389-390, 398-399, 407-408.

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