Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2002-12-31
2004-11-02
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S534000, C327S536000, C327S080000
Reexamination Certificate
active
06812748
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a substrate potential detection circuit generating a substrate potential which is a negative voltage in the semiconductor device.
2. Description of the Background Art
FIG. 10
is a block diagram showing a configuration of a conventional semiconductor device which includes a substrate potential detection circuit
502
.
Referring to
FIG. 10
, a functional circuit
500
included in the semiconductor device requires a substrate potential VBB which is a negative voltage, and must generate a negative voltage internally if no negative voltage is supplied from the outside of the semiconductor device. Therefore, the semiconductor device includes a negative potential generation circuit
504
outputting substrate potential VBB which is a negative voltage, and a substrate potential detection circuit
502
receiving substrate potential VBB, determining whether or not a generated potential is appropriate, and controlling negative potential generation circuit
504
. A charge pump circuit or the like is employed as negative potential generation circuit
504
.
FIG. 11
is a circuit diagram showing a first configuration example of substrate potential detection circuit
502
shown in FIG.
10
.
Referring to
FIG. 11
, substrate potential detection circuit
502
includes an intermediate potential generation circuit
572
receiving substrate potential VBB and outputting a divided potential which is an intermediate potential between a power supply potential VDD and a ground potential, and an inverter
574
receiving the output of intermediate potential generation circuit
572
, determining whether the output is higher or lower than an inversion threshold value, and outputting a control signal /EN.
Intermediate potential generation circuit
572
includes a P-channel MOS transistor
576
having a source and a back gate coupled to power supply potential VDD, a drain connected to a node N
50
and a gate connected to a ground node, and a P-channel MOS transistor
578
having a source and a back gate connected to node N
50
, a drain connected to a ground node and a gate receiving substrate potential VBB. A divided potential, which is an intermediate potential between power supply potential VDD and the ground potential, is outputted from node N
50
.
Inverter
574
includes a P-channel MOS transistor
580
having a source and a back gate coupled to power supply potential VDD, a drain connected to a node N
51
and a gate connected to node N
50
, and a N-channel MOS transistor
582
which is connected between node N
51
and a ground node and which has a gate connected to node N
50
. Control signal /EN is outputted from node N
51
.
FIG. 12
shows the relationship between substrate potential VBB inputted into intermediate potential generation circuit
572
and the divided potential outputted from node N
50
.
Referring to
FIGS. 11 and 12
, if P-channel MOS transistors
576
and
578
have the same electrical characteristic and the following relationship is satisfied, the bias conditions of P-channel MOS transistors
576
and
578
become equal to each other:
VBB=−(½)×VDD.
If the bias conditions of P-channel MOS transistors
576
and
578
become equal to each other, the power supply voltage is divided by these transistors into two. Then, the divided potential outputted from node N
50
becomes (½)×VDD.
Further, if the following relationship is satisfied, the divided potential is lower than (½)×VDD:
VBB<−(
½)×VDD.
On the other hand, if the following relationship is satisfied, the divided potential is higher than (½)×VDD:
VBB>−(½)×VDD.
FIG. 13
shows the input/output characteristics of inverter
574
shown in FIG.
11
.
Referring to
FIGS. 11 and 13
, inverter
574
outputs “H” logic if an input voltage is lower than a logic threshold value, and outputs “L” logic if the input voltage is higher than the logic threshold value.
The logic threshold value of inverter
574
is set at (½)×VDD. Then, substrate potential detection circuit
502
outputs “H” if the following relationship is satisfied:
VBB<−(½)×VDD.
On the other hand, substrate potential detection circuit
502
outputs “L” if the following relationship is satisfied:
VBB>−(½)×VDD.
That is, by setting the electrical characteristics of P-channel MOS transistors
576
and
578
equal to each other and selecting (½)×VDD as the logic threshold value of inverter
574
, substrate potential detection circuit
502
changes an output at a point at which inputted substrate potential VBB coincides with −(½)×VDD. The potential at this point will be referred to as detected potential.
There is a case where a potential other than −(½)×VDD is to be set as the detected potential in the conventional substrate potential detection circuit shown in FIG.
11
. In this case, two methods may be considered. First, if substrate potential VBB becomes a desired value by intentionally setting the electrical characteristic of P-channel MOS transistor
576
and that of P-channel MOS transistor
578
different from each other, a divided potential outputted from node N
50
is made equal to (½)×VDD. Second, the logic threshold value of inverter
574
is changed from (½)×VDD.
To set the electrical characteristic of P-channel MOS transistor
576
and that of P-channel MOS transistor
578
different from each other, such measures as to change the threshold voltage Vth of the P-channel MOS transistors or the resistance value of the channel parts thereof may be taken. However, if the electrical characteristics of transistors are changed by a change in manufacturing conditions or the like, the electrical characteristics of transistors cannot be set different from each other as desired and a desired divided potential cannot be obtained.
Moreover, if the logic threshold value of inverter
574
is changed, the following disadvantage arises. The logic threshold value of an inverter is determined according to the characteristics of both a pull-up element and a pull-down element. Due to this, in a complementary (CMOS) semiconductor device constituted so that a pull-up side is formed by a P-channel MOS transistor and a pull-down side is formed by an N-channel MOS transistor, if the complementary characteristics of the P-channel MOS transistor and the N-channel MOS transistor are changed by a change in manufacturing conditions or the like, a desired logic threshold cannot be obtained.
Under these two circumstances, the conventional art shown in
FIG. 11
has a disadvantage in that a desired detected voltage cannot be stably obtained if an arbitrary potential is selected as a substrate potential.
FIG. 14
is a circuit diagram showing a configuration of a substrate potential detection circuit
502
a
as a second configuration example.
Referring to
FIG. 14
, substrate potential detection circuit
502
a
includes a voltage determination circuit
574
a
in place of inverter
574
in the configuration of substrate potential detection circuit
502
shown in FIG.
11
.
Voltage determination circuit
574
a
includes a reference potential output circuit
586
outputting a reference potential which is a half of power supply potential VDD, and a comparison circuit
588
comparing the output of reference potential output circuit
586
with that of intermediate potential generation circuit
571
and outputting a control signal EN.
Reference potential output circuit
586
includes a P-channel MOS transistor
590
having a source and a back gate connected to power supply potential VDD and a drain and a gate connected to a node N
52
, and a P-channel MOS transistor
592
having a source and a back gate connected to node N
52
and a gate and a drain connected to a ground node. The positive input node of comparison cir
Burns Doane Swecker & Mathis L.L.P.
Cunningham Terry D.
Renesas Technology Corp.
Tra Quan
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