Semiconductor device having structure of copper...

Details Semiconductor device having structure of copper... Semiconductor device having structure of copper...

2000-04-10

2001-09-25

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S760000, C257S762000, C438S624000, C438S639000, C438S687000, C438S777000

Reexamination Certificate

active

06294832

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to the interconnection structure with Cu interconnects and low-k dielectric, and in particular to a semiconductor device having a structure of Cu interconnect/barrier dielectric liner/low-k dielectric trench. The present invention is also related to a method for capping low-k dielectric trenches to reduce the leakage current between separate Cu interconnects, and to prevent Cu from penetration into the low-k dielectric.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a prior art integrated damascene structure with Cu interconnect, low-k dielectric
10
, barrier metal layer
11
, and oxide liner
12
formed on an insulator layer
100
. The barrier metal
11
, and oxide liner
12
composition of TiN, WN, or TaN, serves the purpose of preventing Cu atoms and/or ions from penetration into the low-k dielectric
10
. [E. M. Zielinski, S. W. Russell, R. S. List, A. M. Wilson, C. Jin, K. J. Newton, J. P. Lu, T. Hurd, W. Y. Hsu, V. Cordasco, M. Gopikanth, V. Korthuis, W. Lee, G. Cemy, N. M. Russel, P. B. Smith, S. O'Brien, and R. H. Havemann, in Tech. Dig. IEEE Int. Electron Devices Meeting (IEDM), 936 (1997); H. Aoki, S. Yamasaki, T. Usami, Y. Tsuchiya, N. Ito, T. Onodera, Y. Hayashi, K. Ueno, H. Gomi, and N. Aoto, in Tech. Dig. IEEE Int. Electron Devices Meeting (IEDM), 777(1997); S. C. Sun, in Tech. Dig. IEEE Int. Electron Devices Meeting. (IEDM), 765 (1997); S. C. Sun, M. H. Tsai, H. T. Chiu, S. H. Chuang, and C. E. Tsai, in Tech. Dig. IEEE Int. Electron Devices Meeting. (IEDM), 61 (1995); J. P. Lu, W. Y. Hsu, J. D. Luttmer, L. K. Magel, and H. L. Tsai, J. Electrochem. Soc., 145, L21 (1998); J. P. Lu, W. Y. Hsu, G. A. Dixit, J. D. Luttmer, R. H. Havemann, and L. K. Magel,, J. Electrochem. Soc., 143, L279 (1996); Y. Huang, T. R. Yew, W. Lur, and S. W. Sun, Proc. of 15th VLSI Multilevel Interconnection Conference (VMIC), 33 (1998);] Besides, the oxide liner 12 deposited on trench sidewalls can effectively reduce the leakage current through the low-k dielectric under bias.
The resistivity of barrier metal is generally two to three orders of magnitude higher than that of copper. The barrier metal in the interconnection is obviously not beneficial to lowering the interconnect resistance. Therefore, a thin qualified barrier dielectric liner should be developed to replace both the barrier metal and the oxide liner. In other words, a damascene interconnection in a barrier-metal-free scheme by using the barrier dielectric liner can effectively minimizing the resistance-capacitance time delay [K. Mikagi, H. Ishikawa, T. Usami, M. Suzuki, K. Inoue, N. Oda, S. Chikaki, I. Sakai, and T. Kikkawa, in Tech. Dig IEEE Int. Electron Devices Meeting (IEDM), 365 (1996)], the leakage current and the process complexity.
SUMMARY OF THE INVENTION
The present invention provides a novel technology of barrier dielectric liner, which is prepared by liquid-phase deposition (LPD) and subsequent NH
3
-plasma annealing. The liner is to be applied on damascene interconnection of Cu/low-k dielectric.
A semiconductor device having a structure of Cu interconnect/barrier dielectric liner/low-k dielectric trench fabricated according to the invention, which includes:
a) a substrate;
b) a low-k (k<3) dielectric layer on said substrate, wherein said dielectric layer has a plurality of trenches;
c) a barrier dielectric liner on each sidewall of each trench, wherein said barrier dielectric liner is a nitrogen-containing liquid-phase-deposition (LPD) fluorosilicate glass (FSG) film; and
d) Cu interconnects inlayed in said trenches; wherein
said low-k dielectric layer and said Cu interconnects are separated with said barrier dielectric liner, whose thin surface layer adjacent to said Cu interconnects has a nitrogen concentration within 3-50 atom % and a fluorine concentration within 0.5-10 atom %.
A suitable method for forming a structure of barrier dielectric liner/low-k dielectric trench of the present invention includes the following steps:
A) preparing a silica-supersaturated hydrofluosilicic acid (H
2
SiF
6
) solution;
B) immersing a semiconductor substrate having a plurality of low-k dielectric trenches into the silica-supersaturated H
2
SiF
6
solution prepared in step A), so that a whole surface of said plurality of low-k dielectric trenches is capped with a FSG film, wherein a space between vis-à-vis FSG-capped sidewalls of each trench is preserved for formation of a Cu interconnect;
C) removing the FSG film not on the vis-à-vis sidewalls of each trench by using anisotropic etching; and
D) nitridation of the remaining FSG film on the vis-à-vis sidewalls of each trench from step C) by using NH
3
-plasma annealing for enhancing the barrier property of FSG film to Cu penetration.
Preferably, the method of the present invention further comprises E) forming a Cu interconnect in said space between the vis-à-vis FSG-capped sidewalls of each trench after step D).
Low-k dielectrics applicable to the present invention are methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ) and other similar materials, wherein MSQ is preferable.
For the semiconductor device of the present invention, preferably the bulk part of barrier dielectric liner, i.e. the part outside the thin surface layer, has a fluorine concentration within 6-10 atom %.
For the barrier dielectric liner used in the semiconductor device of the present invention, preferably the depth of its thin surface layer is within 3-30 nm.
Preferably, the nitrogen containing LPD FSG film of the present invention is prepared first by immersing a substrate having a plurality of low-k dielectric trenches into a silica-supersaturated H
2
SiF
6
solution to form a fluorosilicate glass film, and then by annealing the fluorosilicate glass film in NH
3
-plasma ambient. A suitable method for preparing the silica-supersaturated H
2
SiF
6
solution includes elevating a temperature of a silica-saturated H
2
SiF
6
solution for 10° C. or above. Preferably, the temperature of the silica-saturated H
2
SiF
6
. solution is about 0° C., and the elevated temperature of the silica-supersaturated H
2
SiF
6
solution is about 25° C. A suitable method for preparing the silica-saturated H
2
SiF
6
solution includes adding a sufficient amount of silica powder into a H
2
SiF
6
solution having a concentration between 0.5-4.0 M, stirring the resulting mixture at 0° C. for a period of time, and then filtering the mixture for removal of undissolved silica powder.
Preferably, the NH
3
-plasma annealing of the present invention is conducted in a plasma-enhanced chemical vapor deposition reactor under the following conditions: chuck temperature within 25-400° C., chamber pressure within 10-800 mTorr, RF power within 100-1000 W and NH
3
gas flow rate within 100-2000 sccm, and annealing time within 30-7200 sec.
The FSG film formed in step B) of the present invention preferably has a dielectric constant (k) lower than 3.9. More preferably, it has a k value lower than 3.5.
The FSG film formed in step B) of the present invention preferably has a fluorine concentration within 6-10 atom %.
The NH
3
-plasma annealing used in step D) of the present invention preferably forms a thin nitrogen-containing layer on the surface of FSG film, wherein the thin nitrogen-containing layer has a nitrogen concentration within 3-50 atom %, and a fluorine concentration within 0.5-10 atom %. More preferably, the depth of the thin nitrogen-containing layer is within 3-30 nm.


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Zielinski, E.M., et al. “Damascene Integration of Copper and Ultra-Low-k Xerogel for High Performance Interconnects,” IEEE IEDM Tech. Digest, Dec. 1997, pp. 936-938.*
Aoki, H, et al., “A Degradation-Free Cu/HSQ Damascene Technology using Metal Patt

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