Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2007-01-24
2010-06-01
Chambliss, Alonzo (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S758000, C257S774000, C257S786000
Reexamination Certificate
active
07728423
ABSTRACT:
A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to cover the overall surface with respect to ICs, seal rings, and scribing lines. In order to avoid occurrence of breaks and failures in ICs, openings are formed to partially etch insulating layers in a step-like manner so that walls thereof are each slanted by prescribed angles ranging from 20° to 80°. For example, a first opening is formed with respect to a thin-film element section, and a second opening is formed with respect to an external-terminal connection pad.
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Chambliss Alonzo
Dickstein & Shapiro LLP
Yamaha Corporation
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