Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1999-11-03
2004-01-13
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S347000, C257S506000, C257S758000, C257S773000
Reexamination Certificate
active
06677676
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a silicon-on-insulator (hereinafter referred to simply as “SOI”) structure, a method of manufacturing the semiconductor device, and a method of manufacturing a wafer having a SOI structure for use in the semiconductor device.
2. Description of Related Art
Conventionally, an insulation layer is formed on a semiconductor substrate, and semiconductor elements, such as MOS transistors, are fabricated on the insulation layer, thus manufacturing a semiconductor device having what is called a SOI structure. If a semiconductor substrate is in an electrically floating state, electric charges stored in the substrate cannot flow away, and therefore cause changes in the potential of the substrate. This in turn causes the threshold voltage of the MOS transistor to deviate from a desired voltage. To prevent such a deviation from the desired voltage, the potential of the semiconductor substrate must be locked to a steady potential.
To this end, Japanese Patent Application Laid-Open Nos. Hei-3-272176 and Hei-9-223802 propose a semiconductor device, in which contacts are formed so as to extend from a wiring layer to a semiconductor substrate by penetrating through a insulation layer, and a steady potential is supplied to the semiconductor substrate by way of the contacts.
However, according to these prior-art techniques, a contact is formed in an element isolation region between two MOS transistors. More specifically, the contact is formed in an integrated circuit fabricated in the semiconductor device. For this reason, a location for forming a contact must be ensured in the integrated circuit, which may result in an increase in the surface area of the semiconductor device.
Provided that a contact is formed in the integrated circuit, if the contact only connects the semiconductor substrate to the wiring layer as in the case of the prior-art techniques, the number of contacts may increase, which would cause an increase in the surface area of the semiconductor device.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a semiconductor device in which there is avoided an increase in the surface area, which would otherwise be caused by forming contacts for making the potential of a silicon substrate steady.
Another object of the present invention is to provide the structure of a semiconductor device which prevents an increase in the number of contacts.
Still another object of the present invention is to provide a method of manufacturing a semiconductor device at reduced costs by arranging a process of forming contacts for making the potential of a silicon substrate steady.
Yet another object of the present invention is to provide a method of readily manufacturing a semiconductor wafer which comprises a high-concentration semiconductor layer formed on a semiconductor substrate remaining in contact with an embedded insulation film.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; an embedded insulation film formed on one main surface of the semiconductor substrate; an integrated circuit fabricated in a first region on the surface of the embedded insulation film; an interlayer insulation film formed on the embedded insulation film so as to cover the integrated circuit; a wiring layer which includes a portion located outside the first region on the surface of the embedded insulation film, which is formed on the interlayer insulation film, and supplies steady potential; and a contact which is formed at a portion of the wiring layer outside the first region so as to extend to the semiconductor substrate by penetrating through the embedded insulation film and which establishes electrical connection between the wiring layer and the semiconductor substrate.
According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; an embedded insulation film formed on one main surface of the semiconductor substrate; an integrated circuit fabricated on the embedded insulation film; an interlayer insulation film formed on the embedded insulation film so as to cover the integrated circuit; an electrode pad which is formed on the interlayer insulation film so as to be located at a position outside the region on the surface of the embedded insulation film, where an integrated circuit is fabricated; and a contact which is formed so as to extend from the lower surface of the electrode pad to the semiconductor substrate by penetrating through the embedded insulation film and which establishes electrical connection between the semiconductor substrate and the electrode pad.
According to a third aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; an embedded insulation film formed on one main surface of the semiconductor substrate; a MOS transistor fabricated on the surface of the embedded insulation film; an interlayer insulation film formed so as to cover the MOS transistor; a wiring layer which is formed within the interlayer insulation film and supplies steady potential; and a contact having a portion which adjoins a region serving as one terminal of the MOS transistor in side surface, which is formed so as to extend from the wiring layer to the semiconductor substrate by penetrating through the embedded insulation film.
REFERENCES:
patent: 5569621 (1996-10-01), Yallup et al.
patent: 5889306 (1999-03-01), Christensen et al.
patent: 5926703 (1999-07-01), Yamaguchi et al.
patent: 6121659 (2000-09-01), Christensen et al.
patent: 6150694 (2000-11-01), Tihanyi
patent: 3-272176 (1991-12-01), None
patent: 4-343265 (1992-11-01), None
patent: 9-45789 (1997-02-01), None
patent: 9-223802 (1997-08-01), None
patent: 9-223802 (1997-08-01), None
“Threshold Voltage of Thin-Film Silicon-on-Insulator (SOI) MOSFET's”, H. Lim et al., IEEE Transactions on Electron Devices, vol. ED-30, No. 10, Oct. 1983, pp. 1244-1251.
Ueda Kimio
Wada Yoshiki
Lee Eddie
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Warren Matthew E.
LandOfFree
Semiconductor device having steady substrate potential does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having steady substrate potential, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having steady substrate potential will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3220130