Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-01-24
2003-09-16
Clark, Sheila V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S724000, C257S784000
Reexamination Certificate
active
06621156
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a semiconductor device having a Multi Chip Module (MCM) structure and a method of manufacturing such semiconductor device. More particularly, the present invention relates to a semiconductor device and a method of manufacturing such semiconductor device in which a plurality of semiconductor chips are stacked and in which a larger semiconductor chip can be appropriately stacked over a smaller semiconductor chip.
BACKGROUND OF THE INVENTION
Recently, in order to avoid an expansion of mounting area or areas of semiconductor devices and to increase mounting density, there are proposed various types of semiconductor devices having a stacked MCM structure. For example, there is proposed a semiconductor device having a stacked Chip Size Package (CSP) structure in which a plurality of semiconductor chips are closely stacked and mounted on a wiring board or substrate.
FIG. 3
is a cross sectional view showing a conventional semiconductor device having such stacked CSP structure (prior art 1). In the semiconductor device shown in
FIG. 3
, a lower side semiconductor chip
102
is bonded onto a surface of a wiring substrate
101
via insulating adhesive and the like, and an upper side semiconductor chip
103
is stacked and bonded onto the lower side semiconductor chip
102
via insulating adhesive and the like. On the surface of the wiring substrate
101
, there is formed a wiring layer having wiring patterns (not shown in the drawing) On the top surfaces of the lower side semiconductor chip
102
and of the upper side semiconductor chip
103
, there are formed electrodes, i.e., bonding pads,
102
a
and
103
a,
respectively. These electrodes
102
a
and
103
a
are coupled with electrodes
101
a
formed on the wiring substrate
101
via bonding wires
104
and
105
made of gold and the like, respectively, and thereby the lower side semiconductor chip
102
and the upper side semiconductor chip
103
are electrically coupled with the wiring patterns on the wiring substrate
101
.
Also, there are disposed a plurality of solder balls
106
on the backside surface of the wiring substrate
101
. The solder balls
106
are coupled with the wiring patterns formed on the surface of the wiring substrate
101
via holes provided in the wiring substrate
101
(not shown in the drawing). Thereby, the lower side semiconductor chip
102
and the upper side semiconductor chip
103
are electrically coupled with the solder balls
106
. Further, on the wiring substrate
101
, there is formed an encapsulation resin
107
for encapsulating the lower side semiconductor chip
102
, the upper side semiconductor chip
103
and the bonding wires
104
and
105
.
In the semiconductor device mentioned above, the upper side semiconductor chip
103
disposed on the upside is, for example, a memory IC chip, such as a DRAM device and the like. The lower side semiconductor chip
102
disposed on the downside is, for example, a system IC chip, such as a microprocessor and the like. The size of the upper side semiconductor chip
103
is made smaller than that of the lower side semiconductor chip
102
such that the electrodes of the lower side semiconductor chip
102
on the downside can be exposed.
However, according to an advance in semiconductor technology, the feature size of a semiconductor integrated circuit prescribed by the design rule becomes smaller and smaller. Therefore, the size of a semiconductor chip becomes smaller as the feature size becomes smaller while retaining the same function. Thus, according to the reduction of the feature size, there is a possibility that the size of the lower side semiconductor chip
102
becomes smaller than that of the upper side semiconductor chip
103
. In such case, conventionally, the lower side semiconductor chip
102
having a smaller size and the upper side semiconductor chip
103
having a larger size are replaced upside down. That is, the upper side semiconductor chip
103
is mounted on a wiring substrate and the lower side semiconductor chip
102
is mounted on the upper side semiconductor chip
103
. Therefore, conventionally, the semiconductor chip having a smaller size is always used as the upper side semiconductor chip and the semiconductor chip having a larger size is always used as the lower side semiconductor chip, so that when both the semiconductor chips are stacked on a wiring substrate, electrodes, i.e., bonding pads, of the semiconductor chip on the lower side are not hidden by the semiconductor chip on the upper side. Thus, it is possible to couple electrodes of the semiconductor chips on both the upper side and lower side with wiring patterns on the wiring substrate via metal wires.
Japanese patent laid-open publication No. 2000-269408 discloses another type of semiconductor device having a stacked MCM structure, which is hereafter referred to as prior art 2. In the semiconductor device of the prior art 2, interference between semiconductor chips caused by stacking or bonding the semiconductor chips directly are avoided and degree of freedom of wiring of the wiring substrate can be improved.
FIG. 4
is a cross sectional view showing the semiconductor device of the prior art 2. In the semiconductor device shown in
FIG. 4
, on the upper surface of a multi-layer wiring substrate
201
, a lower side semiconductor chip
202
is bonded by using adhesive and the like. Electrodes (not shown in the drawing) formed on the upper surface of the multi-layer wiring substrate
201
are coupled with electrodes (not shown in the drawing) formed on the upper surface of the lower side semiconductor chip
202
via bonding wires
203
. On the upper surface of the lower side semiconductor chip
202
, various circuit elements are also formed. Solder balls
204
are disposed on the under side surface of the multi-layer wiring substrate
201
, and are coupled with multi-layer wiring conductors formed on the upper side surface of the multi-layer wiring substrate
201
via holes formed in the substrate
201
.
Also, on the multi-layer wiring substrate
201
, spacers or dam members
205
are formed which have a height larger than the thickness of the lower side semiconductor chip
202
. On the dam member
205
, lead portions
206
b
of a lead frame
206
are disposed. An upper side semiconductor chip
207
is bonded on a stage portion
206
a
of the lead frame
206
. Also, electrodes (not shown in the drawing) formed on the upper surface, i.e., the surface on which circuits are formed, of the upper side semiconductor chip
207
are connected to the lead portions
206
b
via bonding wires
208
. Further, the lead portions
206
b
and the multi-layer wiring of the substrate
201
are coupled via bonding wires
209
. By this structure, the upper side semiconductor chip
207
is held at a location which is over the lower side semiconductor chip
202
and which is separated from the lower side semiconductor chip
202
, and also the upper side semiconductor chip
207
is electrically coupled with the multi-layer wiring substrate
201
. Further, these upper side semiconductor chip
207
and lower side semiconductor chip
202
, the space between these chips
207
and
202
, the dam members
205
and the bonding wires
203
,
208
and
209
are encapsulated by an encapsulation resin
210
.
However, in the semiconductor device of the above-mentioned prior art 1, when the design rule has changed, it becomes necessary to replace the semiconductor chips upside down. In such case, it is necessary to redesign the wiring substrate and fabricate it again. Therefore, manufacturing costs of the semiconductor device of the prior art 1 become high.
In the semiconductor device of the above-mentioned prior art 2, it is necessary to couple the lead portions
206
b
on the dam member
205
with the multi-layer wiring substrate
201
via bonding wires
209
. Therefore, bonding times become large, and wiring structure becomes complicated. Also, the lead frame
206
for mounting the upper side semiconductor chip
207
is required. Ther
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