Semiconductor device having solid-state image sensor with...

Details Semiconductor device having solid-state image sensor with... Semiconductor device having solid-state image sensor with...

2002-09-03

2003-12-09

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

C438S057000, C438S237000

Reexamination Certificate

active

06660553

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a structure thereof, and more particularly to a method of manufacturing a solid-state image sensor and a structure thereof.
2. Description of the Background Art
FIG. 6
is a circuit diagram showing the structure of a pixel of a conventional CMOS image sensor (cf. S. Inoue et al., “A 3.25 M-pixel APS-C size CMOS Image Sensor”, ITE Technical Report, Vol.25, No.28, pp.37-41). As shown in
FIG. 6
, a pixel of the CMOS image sensor includes a photodiode
101
, a transfer MOS transistor
102
for transferring all of electrons generated in the photodiode
101
to a node FD, a reset MOS transistor
103
for resetting the potentials of the photodiode
101
and the node FD, a source follower MOS transistor
104
for amplifying the potential of the node FD and a select MOS transistor
105
for selecting a line to be read out.
The photodiode
101
has its cathode connected to the source of the transfer MOS transistor
102
. The transfer MOS transistor
102
has its drain connected to both the source of the reset MOS transistor
103
and the gate of the source follower MOS transistor
104
through the node FD. The reset MOS transistor
103
has its drain connected to a power supply for supplying a predetermined power supply potential VDD.
An operation of the conventional CMOS image sensor will be described now. First, gate voltages Vt and Vres are applied to turn on the transfer MOS transistor
102
and the reset MOS transistor
103
, allowing the potentials of the photodiode
101
and the node FD to be reset at the power supply potential VDD. Upon completion of the reset, the application of the gate voltage Vres is stopped to turn off the reset MOS transistor
103
.
Next, all of electrons generated by photoelectric conversion of incident light in the photodiode
101
are transferred to the node FD by the transfer MOS transistor
102
. The potential of the node FD varies in accordance with the amount of electrons as transferred. Next, a gate voltage Vsel is applied to turn on the select MOS transistor
105
. The potential of the node FD as varied is amplified by the source follower MOS transistor
104
to be input to a post-stage readout circuit.
FIG. 7
is a cross-sectional view showing part of the structure of the conventional CMOS image sensor in which the photodiode
101
and the transfer MOS transistor
102
are formed, although illustration of an interlayer insulation film and metallic interconnection is omitted. A P well
111
is formed in an upper surface of the N-type semiconductor substrate
110
. An element isolating insulation film
112
is formed on an upper surface of the P well
111
. In an element forming region defined by the element isolating insulation film
112
, a gate structure
115
having a gate insulation film
113
and a gate electrode
114
laminated in this order is formed on the upper surface of the P well
111
.
In the element forming region, a P
+
-type impurity-introduced region
116
, an N-type impurity-introduced region
117
and an N
+
-type impurity-introduced region
119
are formed in the upper surface of the P well
111
. The N-type impurity-introduced region
117
is formed deeper than the P
+
-type impurity-introduced region
116
. The N-type impurity-introduced region
117
and the P
+
-type impurity-introduced region
116
constitute a photodiode
118
, which corresponds to the photodiode
101
shown in FIG.
6
. Specifically, the anode and cathode of the photodiode
101
shown in
FIG. 6
correspond to the P
+
-type impurity-introduced region
116
and the N-type impurity-introduced region
117
shown in
FIG. 7
, respectively.
Part of the N-type impurity-introduced region
117
(i.e., an end portion on the side of the N
+
-type impurity-introduced region
119
) extends under the gate structure
115
. The N
+
-type impurity-introduced region
119
is opposite to the N-type impurity-introduced region
117
with a channel-forming region under the gate structure
115
interposed therebetween. The gate structure
115
, the N-type impurity-introduced region
117
and the N
+
-type impurity-introduced region
119
constitute an MOS transistor (hereinafter referred to as “MOS transistor X”), which corresponds to the transfer MOS transistor
102
shown in FIG.
6
. Specifically, the gate, source and drain of the transfer MOS transistor
102
shown in
FIG. 6
correspond to the gate electrode
114
, the N-type impurity-introduced region
117
and the N
+
-type impurity-introduced region
119
shown in
FIG. 7
, respectively. The N
+
-type impurity-introduced region
119
also corresponds to the node FD shown in FIG.
6
.
FIG. 8
is a cross-sectional view showing an example of a step of forming the N-type impurity-introduced region
117
. The gate structure
115
has already been formed on the upper surface of the P well
111
. Although not shown in
FIG. 8
, a resist pattern is also formed which has an opening over a region where the N-type impurity-introduced region
117
is to be formed. As described above, part of the N-type impurity-introduced region
117
needs to be formed extending under the gate structure
115
. Thus, when forming the N-type impurity-introduced region
117
, ion implantation of N-type impurities
120
is performed obliquely with respect to the upper surface of the P well
111
while rotating a wafer. The N-type impurities
120
are therefore implanted also under the end portion of the gate structure
115
. Such ion implantation performed obliquely while rotating a wafer is hereinafter referred to as “oblique-rotating implantation” in the present specification.
FIG. 9
is a cross-sectional view showing another example of a step of forming the N-type impurity-introduced region
117
. First, N-type impurities are ion-implanted into the P well
111
from the vertical direction with respect to the upper surface of the P well
111
using the gate structure
115
and the aforementioned resist pattern as an implantation mask, thereby forming an N-type impurity-implanted region
122
. Such ion implantation performed vertically is hereinafter referred to as “vertical implantation” in the present specification. Next, heat treatment is performed excessively as compared to a normal annealing which activates impurities after ion implantation, resulting in excessive thermal diffusion of the N-type impurities in the N-type impurity-implanted region
122
. This causes the N-type impurity-implanted region
122
to extend outwardly and isotropically, so that the consequently obtained N-type impurity-introduced region
117
partly extends under the end portion of the gate structure
115
.
The above-described method of manufacturing the conventional semiconductor device has the following disadvantages in the step of forming the N-type impurity-introduced region
117
.
As shown in
FIG. 8
, the gate electrode
114
actually has a tapered shape. In oblique implantation, the concentration distribution of the N-type impurity-introduced region
117
in the P well
111
varies in accordance with angle A of the taper.
Further, in forming the resist pattern, RCA cleaning may previously be performed in many cases for promoting resist adhesion. A wet process performed at that time may cause an end portion
121
of the gate insulation film
113
to be removed. The concentration distribution of the N-type impurity-introduced region
117
in the P well
111
also varies in accordance with the degree of removal of the end portion
121
of the gate insulation film
113
.
Such variations in the concentration distribution of the N-type impurity-introduced region
117
in the P well
111
not only cause variations in properties of the photodiode
118
but also sometimes cause a potential barrier to occur immediately under the gate electrode
114
, worsening the charge transfer efficiency of the transfer MOS transistor
102
, which disadvantageously causes performance degradation of

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