Semiconductor device having simplified internal data transfer

Details Semiconductor device having simplified internal data transfer Semiconductor device having simplified internal data transfer

2002-03-13

2003-12-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S198000, C365S189050, C327S291000, C327S298000, C327S299000

Reexamination Certificate

active

06671220

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device which receives a plurality of data pieces in synchronization with a plurality of clock signals.
2. Description of the Related Art
A semiconductor device of a synchronous type captures data supplied from an exterior of the device by latching the data in synchronization with a clock signal. In semiconductor memory devices, for example, data captured in this manner is supplied to a core circuit including memory cells and the like. Further, control signals are generated from the clock signal, and are supplied to the core circuit for the purpose of controlling the timing of operations at which the core circuit receives the data. The core circuit controls the timing of operations according to the supplied control signals, and performs operations for storing the data therein among other operations.
FIG. 1
is a block diagram of a related-art configuration of a semiconductor device such as a semiconductor memory device.
FIG. 2
is a block diagram showing a configuration of a block BLK
0
and a block BLK
1
.
As shown in FIG.
1
and
FIG. 2
, the block BLK
0
receives a plurality of clock signals clk
0
, clk
1
, clk
2
, and clk
3
having different timings from an exterior of the semiconductor device
10
, and further receives a plurality of data signals dat
0
, dat
1
, dat
2
, and dat
3
in synchronization with the respective clock signals. Input circuits
12
of the block BLK
0
capture and latch the respective data signals in synchronization with the respective clock signals. Since the data signals dat
0
, dat
1
, dat
2
, and dat
3
are captured in synchronization with the respective clock signals clk
0
, clk
1
, clk
2
, and clk
3
having different timings, the transition timings of the data signals end up being different from each other.
In the block BLK
0
, pulse signal generation circuits
13
generate pulse signals pls
0
, pls
1
, pls
2
, and pls
3
in synchronization with the respective clock signals clk
0
, clk
1
, clk
2
, and clk
3
. These pulse signals pls
0
, pls
1
, pls
2
, and pls
3
have different activation timings from each other. In the block BLK
0
, further, drive circuits
14
transmit the latch data of the input circuits
12
to core circuits
11
at respective transmission timings based on the pulse signals pls
0
, pls
1
, pls
2
, and pls
3
. That is, data pieces DAT
0
, DAT
1
, DAT
2
, and DAT
3
transmitted to the core circuits
11
have different transition timings.
The data pieces transmitted to the core circuits
11
need to be stored in the respective core circuits, so that the respective core circuits
11
require control signals that determine associated data acquisition timings. In order to control a plurality of data pieces DAT
0
, DAT
1
, DAT
2
, and DAT
3
having different transition timings as in the example of FIG.
1
and
FIG. 2
, a plurality of control signals having corresponding timings are required. To this end, the block BLK
1
receives the pulse signals pls
0
, pls
1
, pls
2
, and pls
3
from the block BLK
0
, and generates the pulse signals PLS
0
, PLS
1
, PLS
2
, and PLS
3
, which are then supplied to the core circuits
11
. In the example of
FIG. 1
, two of such blocks BLK
1
are provided.
In order to generate the pulse signals PLS
0
, PLS
1
, PLS
2
, and PLS
3
, some logic operations are performed between a control signal sig and the pulse signals pls
0
, pls
1
, pls
2
, and pls
3
. This control is useful when the core circuits
11
needs to perform data acquisition operation that is dependent on the control signal sig. In order to secure a constant timing margin relative to the pulse signals pls
0
, pls
1
, pls
2
, and pls
3
having different timings, the timing of the control signal sig needs to be shifted according to the timings of the pulse signals pls
0
, pls
1
, pls
2
, and pls
3
. To this end, delay circuits
15
of the block BLK
1
receive the respective pulse signals pls
0
, pls
1
, pls
2
, and pls
3
, and delay the timing of the control signal sig according to the timing of these pulse signals, thereby generating respective control signals sig
0
, sig
1
, sig
2
, and sig
3
. Timing control signal generation circuits
16
receive the respective control signals sig
0
, sig
1
, sig
2
, and sig
3
, and carries out logic operations between these control signals and the respective pulse signals pls
0
, pls
1
, pls
2
, and pls
3
, thereby generating respective pulse signals PLS
0
, PLS
1
, PLS
2
, and PLS
3
. The pulse signals PLS
0
, PLS
1
, PLS
2
, and PLS
3
are supplied through long-distance wires as timing control signals to the respective core circuits
11
, and are used for data storage operations in the core circuits.
FIG. 3
is a timing chart showing the timing of signals described above.
In the example described above, a plurality of data pieces are input from an exterior of the device in synchronization with a plurality of clock signals having respective timings, and are transferred to the core circuits also at respective timings. This requires core circuits that are controlled to operate at the respective timings, which results in a need for a plurality of timing control signals.
When an logic operation is to be applied to the plurality of timing control signals, such a logic operation is needs to be performed in terms of each timing of the timing control signals. This results in the control signals and control circuitry becoming complex, and also results in an increase in circuit size.
Accordingly, there is a need for a semiconductor device which receives a plurality of data pieces in synchronization with respective clock signals wherein control circuitry is reduced in size and complexity by simplifying its timing control.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor device according to the present invention includes input circuits which capture respective data pieces from an exterior of the device in synchronization with respective clock signals supplied from the exterior of the device, a pulse signal generation circuit which generates a pulse signal, and drive circuits which supplies the respective data pieces captured by the input circuits to internal circuitry at a unified timing corresponding to the pulse signal.
The semiconductor device described above transfers incoming data pieces within the semiconductor device at the same transfer timing after the incoming data pieces are input in synchronization with a plurality of clock signals having different timings. Because of this, the internal operation can be controlled based on a single clock signal rather than controlled based on the plurality of clock signals independently of each other. Accordingly, the control circuitry and signal wires that were necessary for each one of different timing arrangements in the related-art configuration can be reduced, thereby simplifying control and reducing circuitry size.
According to one aspect of the present invention, the pulse signal generation circuit merges the clock signals into a single clock signal, and supplies the single clock signal as the puls

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