Semiconductor device having semiconductor memory

Details Semiconductor device having semiconductor memory Semiconductor device having semiconductor memory

2003-04-24

2004-11-23

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Powering

C365S189110

Reexamination Certificate

active

06822921

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and particularly to a semiconductor device having a step-down circuit employed in a read only memory (ROM) encapsulated in a multi-chip package (MCP).
A ROM packaged or encapsulated in a conventional MCP is equipped with a custom chip wherein a logic circuit and a step-down circuit customized to suit user specs are provided on such a general-purpose ROM chip as described in FIG. 1 of the U.S. Pat. No. 6,449,192. Since the size of the custom chip is subjected to constraints of MCP packaging, the chip size becomes larger than an actual circuit scale and hence a lot of empty spaces exist.
As the step-down circuit, there is known one described in FIG. 1 of the U.S. patent application Ser. No. 10/243,644 filed by the present applicant. The disclosed circuit generates a desired internal source or power supply voltage lower than a source voltage. The internal source voltage produced by the step-down circuit is supplied as a power supply for a general-purpose ROM chip through a bonding wire.
The internal source voltage is often used in common with a circuit for supplying a memory cell's drain voltage corresponding to a DC current component, a memory cell and a sense amplifier together with word line control of a general-purpose ROM. There may be a case in which the sharing of such an internal source voltage causes a reduction in internal source voltage, thus leading to a malfunction.
In order to solve such a problem, there is provided Japanese Patent Application Laid-Open No. Hei 11(1999)176181 which discloses that a plurality of internal power-supply generating step-down circuits are provided and supply internal power supplies independently respectively. Here, the voltages of the independent internal power supplies are the same.
In the above-described configuration, however, a problem arises in that an access speed becomes slow if the level of each internal source voltage is lowered to reduce current consumption, whereas if the level of each internal source voltage is raised to increase the access speed, then current consumption increases.
SUMMARY OF THE INVENTION
The present invention aims to provide means wherein a word line-dedicated source electrode is provided in a general-purpose ROM chip, and a step-down circuit dedicated to a word line (hereinafter called “word line-dedicated step-down circuit”) and a step-down circuit excluding the word line (hereafter called “general step-down circuit”) are provided and respectively set to independent potential levels to thereby make compatible a current consumption reduction and an access speed.
The present invention provides a semiconductor device comprising a first semiconductor chip equipped with a semiconductor memory and a second semiconductor chip having a step-down circuit both of which are encapsulated, wherein the first semiconductor chip has a general source pad and a word line-dedicated source pad, and the step-down circuit supplies a first potential to the general source pad and supplies a second potential higher than the first potential to the word line-dedicated source pad.


REFERENCES:
patent: 5329168 (1994-07-01), Sugibayashi et al.
patent: 5363333 (1994-11-01), Tsujimoto
patent: 5805519 (1998-09-01), Tomishima
patent: 6449192 (2002-09-01), Otsuka
patent: 6493282 (2002-12-01), Iida et al.
patent: 11-176181 (1999-02-01), None

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