Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-08-19
2004-08-03
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C361S777000
Reexamination Certificate
active
06770980
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device comprising semiconductor elements packaged on an interposer.
2. Description of the Background Art
Heretofore, in order to reduce the packaging area of semiconductor devices on a circuit substrate, there have been disclosed techniques for laminating a plurality of semiconductor devices comprising semiconductor elements (chips), such as memories, disposed on the substrate called an interposer and for packaging the laminated semiconductor devices on a circuit substrate (e.g., Japanese Patent Laid-Open No. 11-135711).
A conventional semiconductor device will be briefly described below referring to
FIGS. 6
to
8
.
FIG. 6
is a schematic sectional view of a conventional semiconductor device, and
FIG. 7
is a schematic plan thereof. Specifically,
FIG. 6
shows the cross-section along the line X-X in FIG.
7
. Furthermore,
FIG. 8
is a schematic sectional view of a conventional semiconductor device module manufactured by laminating semiconductor devices of FIG.
6
.
In
FIGS. 6
to
8
, the reference numeral
1
denotes a chip (semiconductor element) cut from a wafer;
2
, and
2
A to
2
C denote an interposer (substrate) made of materials such as glass-epoxy base and copper foil;
2
a
denotes the back of the interposer
2
;
2
b
denotes the top surface of the interposer
2
;
3
denotes common electrodes for transmitting common signals to the chip
1
;
3
a
denotes a first chip select electrode (chip select electrode No.
1
);
3
b
denotes a second chip select electrode (chip select electrode No.
2
);
3
c
denotes a third chip select electrode (chip select electrode No.
3
). The reference numeral
4
denotes second electrodes for the common electrodes disposed on the location of the back
2
a
corresponding to the common electrodes
3
;
4
a
denotes a second electrode for the first chip select electrode disposed on the location of the back
2
a
corresponding to the first chip select electrode
3
a
;
4
b
denotes a second electrode for the second chip select electrode disposed on the location of the back
2
a
corresponding to the second chip select electrode
3
b
;
4
c
denotes a second electrode for the third chip select electrode disposed on the location of the back
2
a
corresponding to the third chip select electrode
3
c
;
5
denotes thin metal wires for electrically connecting the chip
1
to the first electrode group;
6
denotes a first wiring for chip selecting;
7
denotes wirings for the common electrode;
7
a
denotes a second wiring for chip selecting;
7
b
denotes a third wiring for chip selecting; and
8
denotes an encapsulating resin for protecting the chip
1
and metal wires
5
, and fixing the chip
1
to the interposer
2
.
As
FIGS. 6 and 7
show, a chip
1
is disposed on substantially the central portion of the surface
2
b
of an interposer
2
. A first electrode group is linearly disposed on the both sides of the chip
1
so as to sandwich the chip
1
. The first electrode group comprises a plurality of common electrodes
3
and a plurality of chip select electrodes
3
a
to
3
c
, and these are solder-ball terminals disposed so as to protrude from the surface
2
b
of an interposer
2
. The a plurality of chip select electrodes
3
a
to
3
c
are disposed on the end region of the first electrode group so as to be adjacent to each other.
Also, as
FIG. 6
shows, a second electrode group is disposed on the back
2
a
of the interposer
2
on the location corresponding to the first electrode group on the surface
2
b
. The second electrode group comprises a plurality of second electrodes
4
for common electrodes and a plurality of second electrodes
4
a
to
4
c
for chip select electrodes, and these are land patterns formed by, for example, photoengraving. The second electrodes
4
for common electrodes on the back
2
a
are disposed on the locations plane-symmetrical to the common electrodes
3
on the surface
2
b
, and the second electrodes
4
a
to
4
c
for chip select electrodes on the back
2
a
are disposed on the locations plane-symmetrical to the chip select electrodes
3
a
to
3
c
on the surface
2
b.
Also, as
FIG. 6
shows, the first chip select electrode
3
a
is electrically connected to the predetermined electrode pad on the chip
1
through a thin metal wire
5
and a first wiring for chip selecting
6
. The second chip select electrode
3
b
is electrically connected to the second electrode
4
a
for the first chip select electrode disposed on the back
2
a
side of the first chip select electrode
3
a
through a second wiring for chip selecting
7
a
. Furthermore, the third chip select electrode
3
c
is electrically connected to the second electrode
4
b
for the second chip select electrode disposed on the back
2
a
side of the second chip select electrode
3
b
through a third wiring for chip selecting
7
b.
On the other hand, the common electrodes
3
are connected to the chip
1
through the thin metal wires and wirings, and also connected to the second electrodes
4
for common electrodes on the back
2
a
through the wirings
7
for common electrodes.
The wirings
7
for common electrodes, the second wiring for chip selecting
7
a
, and the third wiring for chip selecting
7
b
are adopted to connect the first electrodes on the surface
2
b
with the second electrodes on the back
2
a
through through-holes formed in the interposer
2
.
The semiconductor devices thus constituted are laminated, as shown in
FIG. 8
, to form a semiconductor device module. Specifically, the first electrode group formed on the surface
2
b
of the interposer
2
B in the second-level semiconductor device is stacked on the second electrode group formed on the back
2
a
of the interposer
2
A in the first-level semiconductor device. Furthermore, the first electrode group formed on the surface
2
b
of the interposer
2
C in the third-level semiconductor device is stacked on the second electrode group formed on the back
2
a
of the interposer
2
B in the second-level semiconductor device.
The semiconductor device module thus formed is packaged on a circuit substrate (not shown) such as a motherboard. Specifically, the first electrode group in the first-level semiconductor device is stacked on the predetermined electrodes formed on the circuit substrate.
Then, common signals, such as ground signals, address signals, and data signals, are transmitted from the circuit substrate to chips
1
A,
1
B, and
1
C of the first, second and third levels, respectively.
On the other hand, the chip select signals transmitted from the circuit substrate for selecting predetermined chips
1
A to
1
C are transmitted to predetermined chips
1
A to
1
C through predetermined chip select electrodes
3
a
to
3
c.
Specifically, the first chip select signal for selecting the chip
1
A of the first-level semiconductor device transmitted from the circuit substrate is transmitted to the chip
1
A of the first-level semiconductor device through the first chip select electrode
3
a
, the first wiring
6
for chip selecting, and a thin metal wire
5
in the first-level interposer
2
A.
The second chip select signal for selecting the chip
1
B of the second level transmitted from the circuit substrate is transmitted to the chip
1
B of the second level through the second chip select electrode
3
b
, the second wiring for chip selecting
7
a
, and the second electrode
4
a
for the first chip select electrode in the first-level interposer
2
A; and further through the first chip select electrode
3
a
, the first wiring
6
, and a thin metal wire
5
in the second-level interposer
2
B.
The third chip select signal for selecting the chip
1
C of the third level transmitted from the circuit substrate is transmitted to the chip
1
C of the third level through the third chip select electrode
3
c
, the third wiring for chip selecting
7
b
, and the second electrode
4
b
for the second chip select electrode
Cruz Lourdes (Elle)
Cuneo Kamand
McDermott Will & Emery LLP
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