Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-08-30
2003-10-28
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C714S030000
Reexamination Certificate
active
06640198
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a self test function to perform a test using a test program stored in an on-chip memory and random number data. More particularly, the present invention relates to a technique for efficiently performing the test in the case of occurrence of branching to an address space which does not exist on a chip, such as the address space of an external memory.
BACKGROUND OF THE INVENTION
As the speed of processors has been increased, it has become more and more difficult to test processors at an ordinary operation speed (at speed). Especially, in the case of the “system-on-chip” configuration, the processor embedded within the LSI as a core has a core interface which is not connected to an LSI pin, making it difficult to test the processor at speed. In this connection, in recent years, there has been a growing interest in the built-in self test method employing a mechanism in which instructions and random number data are generated at speed within an LSI and the random number data is supplied to a processor, as well as employing a processor instruction execution function in which a signature compressor holds the output responses from the processor.
One technique for realizing the built-in self test method using an instruction execution function owned by a processor is discussed in the 17th VLSI Test Symposium Proceedings in 1999 (pp. 34-40). This technique is hereinafter referred to as “Prior Art Example 1”. This method (technique) comprises hardware for dynamically rewriting a program and a signature compressor for compressing and holding the output of a processor, and divides the program area on a memory into a rewrite-target program and a fixed program. When the rewrite-target program is being executed, instructions and operands are dynamically rewritten, whereas when the fixed program is being executed, operation results stored on the registers are output by use of a store instruction and held by the signature compressor. At the end of the test, an internal state held in the signature compressor is compared with an expected value obtained through simulation beforehand to determine whether the processor is nondefective or defective. In this method, it is possible to change the instruction execution order and operands in order to examine occurrence of various faults. Furthermore, since this method does not require any additional circuit within the processor, it is not liable to suffer lowered performance as compared with the conventional built-in self test method, making it easy to realize at-speed operation. However, this method does not take into consideration processors which access a memory outside the chip through an external memory interface, and therefore does not put any restriction on the address space to be used.
One method for the self test using an on-chip memory performs a self test by use of a cache memory. This method is disclosed in Japanese Laid-Open Patent Publication No. 10-171676 (1998). This method is hereinafter referred to as “Prior Art Example 2”. It should be noted that a built-in self test technique is discussed on pages 73 through 82 of the March issue of IEEE DESIGN & TEST OF COMPUTER in 1993, and on pages 69 through 77 (“A Tutorial on Built-In Self-Test”) of the June issue of the same magazine in 1993.
Prior Art Example 1 (a built-in self test method using an instruction execution function owned by a processor) has a problem in that in the case of processors which access a memory outside the chip through an external memory interface, only on-chip memories can be used in a screening test, making it impossible to efficiently perform the test. For example, in the case of checking branch instructions, since random number data is used, branching to an address in an external memory space which does not exist at the time of the screening test may occur.
Generally, when a branch instruction for branching to an invalid address or undefined code is fetched, the processor executes a series of exception processing codes. Therefore, in Prior Art Example 1, exception processing is frequently carried out, considerably lowering the test efficiency.
On the other hand, to avoid occurrence of exception processing, Prior Art Example 2 uses an address conversion circuit to convert an address signal (which indicates an invalid address) so that it indicates an address in a valid address space of an internal memory. However, in Prior Art Example 2, if this address conversion is applied to a fetch address signal, it is not possible to tell whether the signal indicates the proper branch destination address, making it impossible to sufficiently check the branch instruction function.
As is obvious from the above description, in the case of performing a built-in self test on a microprocessor having an external memory by use of a test program stored in an on-chip memory, in order to efficiently perform the test including a test on a function to use the address space of an external memory, it is necessary to observe generation of an address signal specifying the external memory as well as converting an actual output address signal into a valid address signal.
The present invention relates to a processor performing a built-in self test by use of a program stored in an on-chip memory, and an object of the present invention is to provide a means for observing a signal specifying an address of an external memory when the signal has been generated, and a means for outputting a valid address as an actual address signal in order to efficiently perform the test.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device which includes an on-chip memory and a processor, the processor comprising: a program counter for storing an address in an address space of the on-chip memory and an external memory; a test program counter for storing an address in an address space of the on-chip memory; program counter switching means for, in a test mode, performing control in such a way that when an address of the on-chip memory is detected in the program counter, the address value in the program counter is selected as an address to be accessed in the on-chip memory, whereas when an address of the external memory is detected in the program counter, an address value of the test program counter is selected; and signature compression means for signature-compressing and holding an output value of the program counter.
REFERENCES:
patent: 5189675 (1993-02-01), Nozuyama et al.
patent: 5495486 (1996-02-01), Gheewala
patent: 5732209 (1998-03-01), Vigil et al.
patent: 6240537 (2001-05-01), Sim
patent: 6333706 (2001-12-01), Cummings et al.
patent: 6424926 (2002-07-01), Mak
patent: 10171676 (1999-12-01), None
K. Batcher et al, “Instruction Randomization Self Test for Processor Cores,” 17th VLSI Test Symposium Proceedings, pp. 34-40, 1999.
A Tutorial on Built-In Self-Test, Part 1: Principles, IEEE Design & Test of Computers, pp. 73-82, Mar., 1993.
A Tutoral on Built-In Self-Test, Part 2: Applications, IEEE Design & Test of Computers, pp. 69-77, Jun., 1993.
Hatayama Kazumi
Hikone Kazunori
Kobayashi Seiji
Miyazaki Masahide
Hitachi , Ltd.
Hoff Marc S.
Mattingly Stanger & Malur, P.C.
Raymond Edward
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