Semiconductor device having self-aligned contact

Details Semiconductor device having self-aligned contact Semiconductor device having self-aligned contact

2005-09-21

2009-11-03

Blum, David S (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Mesa structure

C257S638000, C257S629000, C257S646000, C257SE21568

Reexamination Certificate

active

07612433

ABSTRACT:
A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

REFERENCES:
patent: 6303467 (2001-10-01), Jen et al.
patent: 6331472 (2001-12-01), Liu et al.
patent: 6559028 (2003-05-01), Hause et al.
patent: 6784077 (2004-08-01), Lin et al.
patent: 7091105 (2006-08-01), Lee
patent: 7229893 (2007-06-01), Wang et al.
patent: 2005/0040490 (2005-02-01), Park
Article titled “Contact Size Dependence of Highly selective Self-Aligned contact Etching with Polymer Formation and its Mechanism” jointly authored by Liu et al., IEEE/SEMI Advanced Semiconductor Manufacturing conference, pp. 153-156, 2003.

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