Semiconductor device having security technology

Details Semiconductor device having security technology Semiconductor device having security technology

2005-04-26

2005-04-26

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S230080, C365S185040

Reexamination Certificate

active

06885607

ABSTRACT:
Predetermined programs and data are written into a first flash memory. The first flash memory is divided into a plurality of blocks. Security information for the respective blocks of the first flash memory is written into a second flash memory. The security information indicates whether or not reading of the stored data to the outside from the respective blocks of the first flash memory is prohibited. When a read target address signal is output by a CPU, the corresponding read data is read from the first flash memory and supplied to the CPU and a tri-state buffer. As a result, the CPU is able to obtain desired input data. A security signal from the second flash memory is supplied to the control terminal of the tri-state buffer. Accordingly, if reading of data to the outside is prohibited, the read data is not transmitted to the outside.

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patent: 01-232452 (1989-09-01), None
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patent: 2002-007372 (2002-01-01), None
Apr. 15, 2004 Office Action for JP Application No. 2003-076871.

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