Semiconductor device having reduced contact resistance between d

Details Semiconductor device having reduced contact resistance between d Semiconductor device having reduced contact resistance between d

1991-02-11

1992-05-12

James, Andrew J.

357 59, H01L 2978, H01L 2904

Patent

active

051132346

ABSTRACT:
A semiconductor device includes first and second oxide film regions formed on a surface of a semiconductor substrate. A first impurity diffusion region is located at a distance from one of the first and second oxide regions. A second impurity diffusion region is located along the surface of the semiconductor substrate and partially overlaps the first impurity diffusion region. The width of the second impurity diffusion region is greater than that of the first impurity diffusion region. A contact hole is provided extending substantially over the second impurity diffusion region. The contact hole has a first side wall defined by one of the first and second oxide film regions and a second side wall defined by an insulating film. The width of the opening of the contact hole is greater than or equal to the width of the first impurity diffusion region. A conductive film is formed along the bottom portion and along the opposite side walls of the contact hole. A wiring layer is provided connected to the conductive film.

REFERENCES:
patent: 4433468 (1984-02-01), Kawamata
patent: 4477962 (1984-10-01), Godejahn, Jr.
patent: 4512073 (1985-04-01), Hsu
patent: 4935379 (1990-06-01), Toyoshima
"High Speed Bipolar ICs Using Super Self-Aligned Process Technology"; Sakai et al.; Japanese Journal of Applied Physics, vol. 20 (1981) Supplement 20-1, pp. 155-159.

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