Semiconductor device having reduced capacitance to substrate...

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity

Reexamination Certificate

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C438S042000, C438S337000, C438S345000

Reexamination Certificate

active

07087925

ABSTRACT:
In one embodiment, a matrix of free-standing semiconductor shapes are oxidized to form a low capacitance isolation tub. The adjacent rows of shapes in the matrix are offset with respect to each to minimize air gap and void formation during tub formation. In a further embodiment, the spacing between adjacent rows is less than the spacing between shapes within a row.

REFERENCES:
patent: 5742091 (1998-04-01), Hebert
patent: 5844299 (1998-12-01), Merrill et al.
patent: 6034389 (2000-03-01), Burns et al.
patent: 6180995 (2001-01-01), Hebert
patent: 6221727 (2001-04-01), Chan et al.
patent: 6307247 (2001-10-01), Davies
patent: 6661068 (2003-12-01), Durham et al.
patent: 6821840 (2004-11-01), Wieczorek et al.
patent: 2003/0146490 (2003-08-01), Averett et al.

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