Semiconductor device having protected edges

Details Semiconductor device having protected edges Semiconductor device having protected edges

1986-10-16

1988-02-16

James, Andrew J.

357 55, 357 49, 357 58, 357 59, 357 47, 357 50, 357 36, 357 34, H01L 2702

Patent

active

047258748

ABSTRACT:
An N.sup.- silicon layer is epitaxially grown on an oxide film with predetermined openings disposed on one main face of an N.sup.+ silicon substrate to form monocrystalline portions on the openings and polycrystalline portions on the oxide film. Ion implantation and thermal annealing is used to convert the polycrystalline portions to P.sup.+ external base regions and form P.sup.+ internal base regions in the monocrystalline portions. Arsenic ions are selectively implanted into the internal base regions to form N.sup.+ emitter regions. Then, base and emitter electrodes are formed on the external base and emitter regions so as to be electrically insulated from one another by an oxide film and a collector electrode is formed on the other main face of the substrate.

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Jambotkar et al, "Fabrication of Power Transistors," IBM Technical Disclosure Bulletin, vol. 20, No. 10, Mar. 1978, pp. 3977-3979.
Okada et al, "A New Polysilicon Process for a Bipolar Device-PSA Technology," IEEE Transactions on Electron Devices, vol. Ed-26, No. 4, Apr., '79, 385-9.
Sakai et al., "Elevated Electrode Integrated Circuits," Ibid., 379-384.

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