Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
1996-03-25
2001-04-24
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S390000, C257S529000, C257S530000, C257S777000, C257S778000
Reexamination Certificate
active
06222212
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits and in particular to integrated circuits which are programmably configurable or include field programmable elements. This invention also relates to methods for forming such integrated circuits.
2. Discussion of Prior Art
Integrated circuits are manufactured using a sequence of masking steps to form a plurality of transistors, diodes and other active and passive regions in a substrate (typically called a “wafer”) of semiconductor material (typically silicon). Insulating layers and interconnect layers are formed over the surface of the wafer to interconnect the transistors, diodes and active and passive regions. As integrated circuits become more complex, with hundreds of thousands if not millions of transistors on each integrated circuit, the dimensions of the active regions formed in the substrate become smaller. As these dimensions become smaller, more devices can be fabricated on a given area of silicon, but the yield (i.e., the number of useful devices obtained at the end of the manufacturing process divided by the largest number of useful devices theoretically possible) drops for many reasons. These reasons include, for example, processing defects (e.g., particulates, film defects and masking defects), errors in mask alignment, and unwanted impurities in the wafer. With certain complex integrated circuits, as many as 20 to 30 masking steps may be employed and as many as 3 or 4 layers of interconnects may be required in order to produce an operative integrated circuit. Each of the masking steps must be carried out correctly and each of the interconnect layers must be formed as intended to obtain a working integrated circuit.
As the sizes of integrated circuits are increased, the yield drops, thereby increasing the costs of the resulting functional integrated circuits. Moreover, as the number of masking steps and interconnect layers increases, the time required to obtain a finished integrated circuit increases because each of the fabrication steps must be carried out sequentially.
Existing field programmable semiconductor devices, such as EPROM, EEPROM, flash memory, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), erasable programmable logic devices (EPLDs), and fuse PROM are manufactured by conventional semiconductor fabrication processes, whereby the devices are fabricated by a plurality of sequential semiconductor processing steps. As previously described, the sequential nature of these processing steps reduces the process yield. Moreover, the field programmable elements used in the field programmable semiconductor devices complicate the overall process as compared to standard semiconductor processes used to make, for example, conventional logic elements such as logic gates. As a result, the process used to manufacture field programmable semiconductor devices is generally more complex, and therefore more costly, than the process used to manufacture conventional logic elements. Furthermore, the technology required to fabricate field programmable elements is often not compatible with the standard technology required to fabricate conventional logic elements. This incompatibility results, at least in part, from the high voltages and/or currents used to program the field programmable elements. As a result, trade-offs must be made in parameters such as design layout, process film thickness and junction depth, for example, in order to allow both the field programmable elements and the logic elements of the field programmable semiconductor devices to be fabricated on the same wafer. The result of these trade-offs is a field programmable semiconductor device which performs more poorly than a device fabricated using separate design rules.
Accordingly, it is desirable to have a method and structure which reduces the manufacturing time associated with the fabrication of an integrated circuit. It is also desirable to have a method and structure which reduces the complexity of the fabrication process required to make complex integrated circuits, particularly field programmable semiconductor devices. It is also desirable to have a method and structure which allows optimal design rules to be utilized in the manufacture of integrated circuits which include both conventional logic elements and field programmable elements.
SUMMARY OF THE INVENTION
In accordance with the present invention, the manufacture of integrated circuits is substantially simplified by using parallel processes to manufacture selected parts of the integrated circuits. The time required to manufacture a completed integrated circuit is significantly reduced because the selected parts are manufactured in parallel.
In one embodiment of the invention, an integrated circuit structure includes a base semiconductor structure and a programmable semiconductor structure. The base semiconductor structure contains active and passive semiconductor regions which are used in the finished integrated circuit structure. The programmable semiconductor structure is formed separately from the base semiconductor structure and is joined to the base semiconductor structure to form the integrated circuit structure. The programmable semiconductor structure contains at least one programmable element. In one embodiment, the programmable element is programmable to control the configuration of the integrated circuit structure. In another embodiment, the integrated circuit structure is a field programmable logic device, and the programmable element is a field programmable element.
Because the base semiconductor structure and the programmable semiconductor structure are fabricated separately, different design rules can be used in the fabrication of these structures, thereby optimizing the performance of both the base semiconductor structure and the programmable semiconductor structure.
In different embodiments, the programmable elements formed in the programmable semiconductor structure can include fuses, anti-fuses, EPROM cells, EEPROM cells, ferro-logic devices or a combination thereof.
In a particular embodiment of the invention, a plurality of electrically conductive first contact elements are connected to the active and passive regions of the base semiconductor structure. Additionally, a plurality of electrically conductive second contact elements are connected to the programmable elements. The first contact elements are exposed at a first surface of the base semiconductor structure and the second contact elements are exposed at a first surface of the programmable semiconductor structure. When the base semiconductor structure is joined to the programmable semiconductor structure, the first contact elements are electrically connected to the second contact elements, thereby forming the integrated circuit structure.
Several alternatives are provided for forming bonding pads on the integrated circuit structure. In one embodiment, the first surface of the base semiconductor structure includes a bonding pad region which extends laterally beyond the lateral perimeter of the first surface of the programmable semiconductor structure when the base semiconductor structure and the programmable semiconductor structure are joined. Bonding pads are formed over the bonding pad region and electrically conductive elements connect the bonding pads to the contact elements.
In another embodiment, the first surface of the programmable semiconductor structure includes a bonding pad region which extends laterally beyond the lateral perimeter of the first surface of the base semiconductor structure when the base semiconductor structure and the programmable semiconductor structure are joined. Bonding pads are formed over the bonding pad region and electrically conductive elements connect the bonding pads to the contact elements.
In yet another embodiment, bonding pads are formed on a second surface of the programmable semiconductor structure which is opposite the first surface of the programmable semiconductor structure. Elect
Hansen Anita
Lee Ji-Min
Lien Chuen-Der
Perham Leonard
Santandrea Joseph F.
Bever Hoffman & Harms LLP
Integrated Device Technology Inc.
Mintel William
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