Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-09-09
2004-04-27
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S670000
Reexamination Certificate
active
06727578
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuit devices, and more particularly to power supply circuits for semiconductor integrated circuit devices.
BACKGROUND OF THE INVENTION
The operation of most semiconductor integrated circuit devices relies on the application of a high power supply voltage and low power supply voltage. Such supply voltages allow nodes to be driven according to voltage and current switching actions, and thus provide the desired device functions. In addition, such supply voltages often serve to maintain a reverse bias condition at p-n junctions within the substrate. This allows circuit devices of opposite conductivity types, such as n-channel and p-channel metal(conductor)-oxide(insulator)-semiconductor (MOS) transistors, to be formed within the same semiconductor layer.
Conventionally, an integrated circuit device (sometimes referred to as a “die” or “chip”) is formed on and within a portion of a silicon wafer (also referred to as a “slice”). The die is then placed into some sort of package that provides electrical access to the die. Many types of packages will include a “lead frame.” A lead frame typically includes a die paddle, which provides a planar surface for physically holding the die, and a number of conductive leads, which carry electrical signals to the die. The die is attached to the die paddle by a die attach material. The leads are then attached to the die by conductive bond wires. Thus, with such an arrangement, the high and low power supply voltages are then applied to the die by connecting selected leads to the power supply voltages. The power supply voltages are then carried to the die by their associated bond wires. Other signals, such as input and output signals, can be carried to and from the die by bond wire/lead combinations.
On the die itself, the bond wires are connected to the die at exposed portions of a conductive layer referred to as “bond pads.” In the case of power supply voltage bond pads, the power supply voltages are carried from the associated bond pads to various locations within the die by patterned conductive layers. Because of the dense arrangement of most integrated circuits, the power supply wiring requirements can often result in one conductive layer carrying one power supply voltage, while a second conductive layer carries the other power supply voltage.
It is also noted that the physical area required for bond pads can be considerable. Bond pads are relatively large structures as they must provide sufficient area for a bond wire to make a low resistance ohmic contact with a conductive layer on the die. Any approach to semiconductor device packaging that can reduce the number of bond pads would free up valuable area on the die. Such extra area can provide for more relaxed signal routing and device placement requirements.
Because a low power supply voltage (which is typically zero volts or “ground”) is often used to establish a signal value (i.e., ground representing a logic “0” while the high power supply represents a logic “1”) it is important to have a low resistance to ground within a semiconductor device. In the event the resistance is too high, the discharge of a large capacitive load through the device (via a lead frame pin, for example) can lead to “ground bounce.” Ground bounce results in the ground power supply potential rising above the zero volts level, and thus result in an erroneous signal value. The inherent inductance within the package wiring can also add to ground bounce effects.
High resistance paths to power supply voltages can also result in higher power consumption rates when nodes within a semiconductor device are charged and discharged.
Referring now to
FIG. 1
, a side cross sectional view of a portion of a prior art integrated circuit is set forth. The portion is designated by the general reference character
100
and illustrates an n-well complementary MOS (CMOS) arrangement. The integrated circuit portion
100
is formed on a relatively highly doped p-type substrate
102
. According to well-known techniques, an epitaxial layer of relatively lightly doped p-type silicon
104
is grown over the substrate
102
. An n-type well
106
is then formed within the epitaxial layer
104
. Isolation structures
108
are formed within the epitaxial layer
104
and n-well
106
, and thereby define “active areas” in the surface of the semiconductor device. Circuit devices, such as transistors or the like, can then be formed in the active areas. The isolation structures
108
may be formed from a variety of isolation techniques, including the local oxidation of silicon (LOCOS) or silicon trench isolation (STI). Active areas within the epitaxial layer
104
include relatively highly doped p-type regions
110
and n-type regions
112
. Similarly, the n-well
106
active areas also include relatively highly doped n-type regions
114
and p-type regions
116
.
In a CMOS device, the p-type epitaxial layer
104
will be biased to a low power supply voltage. This is conventionally accomplished by coupling the epitaxial layer
104
to the low power supply voltage by way of a contact, such as the highly doped p-type region
110
. Similarly, in order to maintain the n-well
106
at a reverse biased state with respect to the epitaxial layer
104
, the n-well
106
will be biased to a high power supply voltage. Conventionally, this is accomplished by coupling the n-well
106
to a high power supply voltage by way of a contact, such as the highly doped n-type region
114
. It is these types of biasing requirements that can result in dense power supply wiring requirements.
As noted above, the power supply wiring requirement can result in larger device sizes, due to the number of power supply contacts required. In addition, the need for low resistance paths to power supplies (to avoid ground bounce and reduce power consumption) and dense wiring constraints, can force multiple wiring layers, adding to the complexity and/or cost of the semiconductor device.
In light of the above drawbacks in existing power supply circuits, it would be desirable to have a power supply circuit arrangement that provides for a more compact and/or less complex semiconductor device.
Another aspect of semiconductor device packaging and operation arises out of the increasingly higher operating speed of such devices. In a conventional packaging arrangement, a bond wire carries the low power supply voltage to a conductive layer on the semiconductor device. Other signals, that vary in potential with respect to the low power supply level, are carried to the device by other bond wires. At lower frequencies (operating speeds) conventional packaging arrangements may provide sufficient performance. However, at higher frequencies transmission line effects can come into play, and it may be desirable to have specialized packaging that addresses such effects. Such “transmission line” wiring approaches often rely on the presence of a “ground” plane, such as a planar conductor coupled to the ground voltage. Unfortunately, conventional packaging arrangements are not conducive to such specialized wiring approaches, and do not provide a ground plane.
It would be desirable to provide an integrated circuit semiconductor device packaging arrangement that is conducive to transmission line-type wiring approaches.
Yet another aspect of semiconductor integrated circuits is that of signal routing. In more complex semiconductor devices, complex conductive layer wiring is often required. Such wiring is necessary, not only to ensure that circuit portions are properly connected, but that such connections have sufficiently low resistance and capacitance. Such wiring requirements often give rise to semiconductor devices with two or more metallization layers. Such additional conductive layers can add to the complexity and expense of the manufacturing process. In addition, such additional conductive layers can introduce a higher number of failing devices (reduce “yield”).
Any approach to semiconductor devices that can reduce the co
Lin Heng-Chih
Scott David B.
Brady III Wade James
Nadav Ori
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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