Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-06-18
2004-04-13
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S226000
Reexamination Certificate
active
06721232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor memory having a delay locked loop (DLL) circuit mounted thereon.
2. Description of the Background Art
In recent years, the operations of semiconductor devices have been increasingly accelerated. As one of the semiconductor devices required to perform high rate operation, there is known a double data rate synchronous dynamic random access memory (DDR SDRAM).
DDR SDRAM can transmit data in a cycle half as long as that of an external clock signal. It is a standard that DDR SDRAM outputs data at timing synchronous with the rising edge and the falling edge of an external clock signal. If data is outputted with the external clock signal used as a trigger, an internal delay occurs to DDR SDRAM and DDR SDRAM cannot satisfy this standard. To satisfy the standard, a DLL circuit is mounted on DDR SDRAM.
FIG. 21
is a block diagram for explaining a conventional DLL circuit
516
.
Referring to
FIG. 21
, DLL circuit
516
delays clock signals BUFFCLK and BUFFZCLK applied from the outside of DLL circuit
516
by a fixed delay and a variable delay to generate clock signals CLKP and CLKN for data output, respectively. DLL circuit
516
then feeds back clock signal CLKP applied to a DQ buffer
514
, compares the phase of clock signal CLKP thus fed back with that of clock signal BUFFCLK applied from the outside of DLL circuit
516
and thereby adjusts a variable delay quantity. As a result, if data is outputted synchronously with data output clock signal CLKP, it is possible to always synchronize the phase of the clock signal applied from the outside thereof with that of the outputted data.
Complementary clock signals are inputted into DDR SDRAM from the outside of DDR SDRAM. Therefore, DLL circuit
516
receives clock signals BUFFCLK and BUFFZCLK corresponding to the complementary clock signals applied from the outside of DDR SDRAM, respectively.
DLL circuit
516
includes delay lines
532
and
533
which receive and delay clock signals BUFFCLK and BUFFZCLK, respectively. Delay line
532
delays clock signal BUFFCLK in accordance with control signals A[
2
:
0
] and outputs clock signal CLKP. Delay line
533
delays clock signal BUFFZCLK in accordance with control signals A[
2
:
0
] and outputs clock signal CLKN.
DLL circuit
516
also includes a replica buffer
534
which delays clock signal CLKP by a predetermined quantity and outputs clock signal FBCLK so as to feed back clock signal CLKP, and a phase comparison circuit
538
which compares the phase of clock signal BUFFCLK with that of clock signal FBCLK and outputs control signals A[
2
:
0
] in accordance with the phase difference.
DQ buffer
514
outputs data which is to be outputted at the timing of the rising edge of an external clock signal, synchronously with the rising edge of clock signal CLKP. In addition, DQ buffer
514
outputs data which is to be outputted at the timing of the falling edge of the external clock signal, synchronously with the rising edge of clock signal CLKN.
As described above, DLL circuit
516
is required to feed back data output clock signal CLKP so as to make the phase of the external clock signal coincident with that of outputted data. According to the configuration shown in
FIG. 21
, only clock signal CLKP out of data output clock signals CLKP and CLKN is fed back to DLL circuit
516
and the phase comparison result of phase comparison circuit
538
is shared between delay lines
532
and
533
for adjusting the variable delay quantities thereof, respectively. By doing so, it suffices to provide only a pair of a phase comparison circuit and a replica buffer, making it possible to suppress a layout area from increasing.
However, if the variable delay of each of delay lines
532
and
533
is realized by inverters, a problem sometimes arises due to the fact that only clock signal CLKP is fed back to DLL circuit
516
. For example, the two delay lines slightly differ in operating power supply voltage.
FIG. 22
is an explanatory view for the problem of the conventional DLL circuit.
Referring to
FIG. 22
, delay lines
532
and
533
which receive complementary clock signals BUFFCLK and BUFFZCLK, respectively, are supplied with a power supply potential VDD
4
from a power supply generation circuit
572
. Power supply generation circuit
572
is normally provided to be dedicated to the DLL circuit, receives an external power supply potential of, for example, 2.5 V and generates 2.1V as power supply potential VDD
4
.
It is assumed herein that, as shown in
FIG. 22
, delay line
533
is supplied with the power supply potential from power supply generation circuit
572
by way of power supply lines PSL
11
and PSL
12
and that delay line
532
is supplied with the power supply potential by way of power supply lines PSL
11
and PSL
13
.
In
FIG. 22
, power supply lines PSL
12
and PSL
13
differ in length. If the lengths of power supply lines PSL
12
and PSL
13
differ, the resistance of power supply line PSL
12
differs from that of power supply line PSL
13
. As a result, there is a probability that the power supply potential supplied to delay line
532
slightly differs from that supplied to delay line
533
.
In that case, even if the clock signals are adjusted to be passed through the same number of inverters using the same control signals A[
2
:
0
], the delay quantity of delay line
533
differs from that of delay line
532
. For example, it is assumed that the power supply potential of one of the delay lines is lowered by 0.05V and the delay quantity of the delay circuit per inverter relatively increases by 5 ps. In this case, if 100 inverters are used for the delay line, the phases of the two delay lines are shifted by as much as 500 ps. In other words, although the phase difference between complementary clock signals BUFFCLK and BUFFZCLK is 180°, the phase difference between data output clock signals CLKP and CLKN is deviated from 180°.
Since clock signal CLKP is always fed back to DLL circuit, it is possible to make the phase of the data outputted at the timing of the rising edge of clock signal CLKP coincident with that of the external clock signal. However, since the phase difference between clock signals CLKP and CLKN is deviated from 180°, the phase of the data outputted at the timing of the rising edge of data output clock signal CLKN is not coincident with that of the external clock signal. This makes it difficult to satisfy the standard for data output timing.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of outputting appropriate clock signals complementary to each other in phase if a DLL circuit which feeds back only one of the complementary clock signals so as to decrease a layout area is mounted on the semiconductor device.
In short, according to one aspect of the present invention, there is provided a semiconductor device which includes a delay locked loop circuit and a potential supply section.
The delay locked loop circuit generates first and second internal clock signals in accordance with first and second external clock signals complementary to each other and applied from an outside, respectively.
The delay locked loop circuit includes first and second variable delay circuit, a delay circuit and a phase comparison circuit. The first variable delay circuit delays the first external clock signal, and outputs the first internal clock. The second variable delay circuit delays the second external clock signal, and outputs the second internal clock signal. The delay circuit receives and delays the first internal clock. The phase comparison circuit compares a phase of an output of the delay circuit with a phase of the first external clock signal, and outputs a control signal according to a phase difference to the first and second variable delay circuits.
The potential supply section is connected to the first variable delay circuit, connected to
Auduong Gene
McDermott & Will & Emery
Renesas Technology Corp.
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