Semiconductor device having offset twisted bit lines

Details Semiconductor device having offset twisted bit lines Semiconductor device having offset twisted bit lines

1999-09-22

2001-06-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

Magnetic

C365S063000, C365S051000

Reexamination Certificate

active

06249452

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to lines that carry data in semiconductor integrated circuit devices, and more particularly to densely packed data lines in such devices.
BACKGROUND OF THE INVENTION
The fabrication of semiconductor devices typically includes the depositing and patterning of insulating layers and conductive layers. In general, the fabrication of a device can start with the patterning of a semiconductor substrate into active area portions separated from one another by insulation. Subsequent alternating insulation and conductive layers are then formed over, and sometimes coupled to the substrate, to interconnect the various circuit elements within the device (such as transistors, capacitors, resistors and the like).
The patterning of an insulating or conductive layer can be accomplished using a lithography and etch step. The lithography step involves depositing an alterable material, referred to as a “resist” on the layer that is to be patterned. The resist is then “developed” or “printed” into a pattern by the application of some form of radiation. For example, “photoresists” can be patterned by the application of light. Other resists can be patterned by x-rays, electron beams or ion beams, to name just a few examples. The pattern within a resist is typically developed by situating a “mask” containing the desired pattern over the resist. The mask includes “transparent” portions that will allow radiation to pass through, and “blocking” portions that will block the radiation. When the radiation is applied, the areas of resist situated below the transparent mask portions will be developed while those below blocking portions will not be developed. The undeveloped portions of resist can then be removed with a solvent, leaving the desired pattern over the fabrication layer. In the case of photolithography, the developing of resist will depend on the intensity of the light applied to the resist.
The developed pattern of resist can then serve as an etch mask for the fabrication layer below. An etch can be applied, and those portions of the fabrication layer that are covered by the etch mask will be protected from the etch. The exposed portions of the fabrication layer will be removed. In this manner, structures or “features” are formed in the fabrication layer by the etch step. For example, in the event the fabrication layer is a conductive layer, the etch step can create conductive interconnects between various portions of a device. In the event the fabrication layer is an insulation layer, the etch step can create contact holes through the insulation layer to a conductive layer below.
In order to fabricate as small a semiconductor device as possible, and hence produce such devices in a more cost-effective manner, efforts are continually made to form features with as small a size as possible. The smallest manufacturable feature size is often referred to as a minimum feature size. The minimum feature size will determine how close structures can be situated relative to one another in the semiconductor device. In addition to impacting the resulting size of a semiconductor device, feature sizes can also affect the functionality of a semiconductor device. For example, in order to create accurate etch mask patterns from a layer of resist, sufficient radiation must be applied to the resist to print the pattern. However, as masks are made for devices having increasingly smaller features sizes, it becomes more and more difficult to control the resulting radiation intensity necessary to produce uniform feature sizes across a semiconductor device.
A drawback to prior art conventional photolithography approaches is set forth in FIG.
1
.
FIG. 1
includes a portion of a photolithography mask
100
(“photomask”) that includes transparent portions
102
and blocking portions
104
. Ideally, the two transparent portions
102
would create two distinct intensity patterns, and thus produce two adjacent features. Set forth below the photomask
100
is a first graph
106
illustrating the amplitude of the light waveforms that result from the photomask
100
. Below the first graph
106
is a second graph
108
setting forth the resulting light intensity provided by the photomask
100
transparent portions
102
. The intensity graph
108
shows that when smaller feature sizes are required, it is difficult to achieve two distinct intensity waveform, and thus two distinct features.
FIG. 2
illustrates one approach to producing smaller features sizes using the same light wavelength as that shown in FIG.
1
.
FIG. 2
includes a photomask
200
having transparent portions
202
a
and
202
b,
as well as blocking portions
204
. However, unlike the photomask
100
of
FIG. 1
, the photomask
200
of
FIG. 2
is a phase-shifted photomask. Thus, while the transparent portions (
202
a
and
202
b
) allow light to pass through, transparent portion
202
b
introduces a phase shift in the light with respect to transparent portion
202
a.
The phase shift may be accomplished by making the transparent portion
202
b
from a different material, different combination of materials, or a different thickness than transparent portion
202
a.
The resulting light amplitude response of the phase-shift mask
200
is set forth in a first graph
206
. As shown, the light provided by transparent portion
202
b
is shifted in phase, by approximately 180°, from that provided by transparent potion
202
a.
The resulting light intensity is shown in a second graph
208
. As shown in the second graph
208
, the phase shift causes the resulting intensity between the two peaks to be less, due to interference effects. Consequently, a better intensity profile, and hence better resist etch mask can be created. In this manner, phase shifted masks can create smaller minimum feature sizes than conventional (non phase-shifted) lithography approaches. It is noted however, that adjacent features must be patterned by using light of opposing phases.
One particular type of semiconductor device in which minimum feature sizes can play an important role is the semiconductor memory device. Semiconductor memory devices typically ihclude an array of densely packed memory cells that are connected to one another by conductive lines. In most random access memory (RAM) and read-only-memory (ROM) configurations, the memory cells are arranged in rows and columns. Densely packed conductive lines are disposed over the memory cells and can include bit lines, extending in the column direction, and word lines extending in the row direction. In order to provide as dense a device as possible, it is advantageous to make the conductive lines with as small a feature size as possible.
Conventional bit line layouts (i.e., a series of parallel lines) can benefit from phase-shifted mask approaches by alternating the phase of the light used to pattern adjacent bit lines. For example, the light used to pattern even bit lines could be at one phase, while the phase of light used to pattern odd bit lines is shifted by 180°. Unfortunately, for more complex bit lines, phase-shifted masks may not be applicable.
An example of a bit line arrangement that is not conducive to phase shifted masks is set forth in FIG.
3
. The bit line arrangement of
FIG. 3
is a “triple twist” bit line arrangement, and is designated by the general reference character
300
. The arrangement
300
is shown to include first twisted bit line pairs (
302
a
and
302
c
) and a second twisted bit line pair
302
b.
The bit line pairs (
302
a
and
302
b
) are considered “twisted” in that the orientation of the bit lines within each pair switches with respect to one another. For example, the bit line pair
302
a
includes a first bit line
304
a
and a second bit line
304
b.
Toward the top of the figure, bit line
304
a
is to the left of bit line
304
b.
Toward the bottom of
FIG. 3
, bit line
304
a
is to the ,right of bit line
304
b.
In a similar fashion, bit line pair
302
b
includes a first bit line
304
c
that is disposed to the left of a second bit line
30

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