Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1997-10-17
1999-03-16
Le, Vu A.
Static information storage and retrieval
Addressing
Plural blocks or banks
365239, 36523004, G11C 700
Patent
active
058838481
ABSTRACT:
A semiconductor memory device is provided that enhances data output speed. The semiconductor uses dual memory arrays with differing activation voltage levels. The semiconductor memory includes a first memory cell array having multiple memory cells and a second memory cell array having more memory cells than the first memory cell array. First and second row decoders respectively receive first and second row addresses to respectively generate an activation signal for a word line in the first memory cell array and subsequent word lines in the second memory cell array. A column decoder receives and decodes a column address to generate a bit line selection signal for the first and second memory cell arrays. The semiconductor device further includes a sense amplifier, which is coupled to bit lines selected based on the bit line selection signals, that detects a potential difference between the bit lines caused by data and amplifies the potential difference. The sense amplifier also refreshes the data on the memory cell from which the data was read.
REFERENCES:
patent: 5691955 (1997-11-01), Yamauchi
patent: 5748555 (1998-05-01), Park
Jun Young-Hyun
Kim Tae-Hyoung
Le Vu A.
LG Semicon Co. Ltd.
LandOfFree
Semiconductor device having multiple sized memory arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having multiple sized memory arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having multiple sized memory arrays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-823254