Semiconductor device having multiple layer resistance layer stru

Details Semiconductor device having multiple layer resistance layer stru Semiconductor device having multiple layer resistance layer stru

1989-07-11

1992-03-03

James, Andrew J.

357 4, 357 6, 357 51, 357 54, H01L 2702

Patent

active

050937065

ABSTRACT:
A high load resistance type static random access memory (SRAM) is provided, as an example of a semiconductor device having a high resistance layer. The SRAM includes a semiconductor substrate (1) of a first conductivity type with an impurity diffusion region (3) of second conductivity type selectively formed thereon. An aluminum interconnection layer (8) is formed over the impurity diffusion region (3). Provided between the aluminum interconnection layer (8) and the impurity diffusion region (3) is a double-layer high resistance structure which comprises a nitride layer (63a) formed adjacent the semiconductor substrate (1) and an oxide layer (63b) adjacent the aluminum interconnection layer (8). The impurity diffusion region (3) forms part of a MOS field effect transistor, which is coupled to the high resistance layer (63) to form a flip-flop memory cell. The double-layer high resistance structure makes it possible to adjust the resistance at a desired particular high value by controlling the thickness of the layer. The structure permits a high degree of integration of the SRAM. The high resistance layer is not affected by diffusion or penetration of the impurity thereto.

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Frohman-Bentchkowsky et al., "Charge Transport and Storage in Metal-Nitride-Oxide-Silicon (MNOS) Structures," Jul., 1969, Journal of Applied Physics, vol. 40, No. 8, pp. 3307-3319.

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