Semiconductor device having multilevel wiring with improved plan

Details Semiconductor device having multilevel wiring with improved plan Semiconductor device having multilevel wiring with improved plan

1997-01-13

1999-09-21

Kelley, Nathan

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257752, H01L 2348

Patent

active

059557885

ABSTRACT:
A semiconductor device having metal wirings in two or more layers has a slit formed in the metal wiring which is a lower layer, and a SOG film flows into the slit while forming the SOG film. The film thickness of the SOG film formed on the metal wiring of a large area differs little from that of the SOG film formed on the metal wiring of a small area. Therefore, a grade of flatness of an interlayer insulating film disposed between the metal wirings is not deteriorated. A humidity resistant property and an electromigration resistant property are not degraded.

REFERENCES:
patent: 5329162 (1994-07-01), Nadaoka

Affiliated with

Also associated with

Rating

Semiconductor device having multilevel wiring with improved plan does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having multilevel wiring with improved plan, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having multilevel wiring with improved plan will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-82922