Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2006-12-26
2006-12-26
Le, Dung A. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S758000, C257S775000, C257SE23145, C257SE21576, C438S618000, C438S622000
Reexamination Certificate
active
07154183
ABSTRACT:
A semiconductor device having a multilevel interconnection encompasses (a) a subject level interconnect, (b) a subject interlevel insulator disposed on the subject level interconnect, (c) a connecting via-plug buried in the subject interlevel insulator, the bottom surface of the connecting via-plug is in contact with the subject level interconnect, (d) a dummy via-plug buried in the subject interlevel insulator, the top surface of the dummy via-plug is electrically open, and (e) an upper level interconnect of the subject level interconnect, disposed at the top surface of the subject interlevel insulator, being contact with the top surface of the connecting via-plug.
REFERENCES:
patent: 6468894 (2002-10-01), Yang et al.
patent: 2004/0113238 (2004-06-01), Hasunuma et al.
patent: 2004/0173905 (2004-09-01), Kamoshima et al.
patent: 2001-196372 (2001-07-01), None
K. Yoshida et al., “Stress-Induced Voiding Phenomena for an actual CMOS LSI Interconnects,” International Electron Devices Meeting, Dec. 2002.
Foley & Lardner LLP
Kabushiki Kaisha Toshiba
Le Dung A.
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