Patent
1983-06-09
1986-06-10
James, Andrew J.
357 71, 357 65, 357 54, 29591, H01L 2348
Patent
active
045946060
ABSTRACT:
A semiconductor device having a multilayer wiring structure with improved interlayer connections comprises a semiconductor substrate with a first insulating layer provided on a major surface of the substrate; a first extended wiring layer of, for example, polycrystalline silicon, formed on the first insulating layer and preferably having an essentially rectangular cross-sectional shape; a second insulating layer provided on the first insulating layer and on the first wiring layer; a contact hole provided in the second insulating layer to expose a contact region of the first wiring layer and having a width greater than the width of the contact region; a third insulating layer formed in the contact hole in contact with the sidewalls of the contact region and having a thickness which decreases in height smoothly and gradually in a direction away from the respective contact region sidewalls; a second extended wiring layer of, for example, aluminum formed on the second insulating layer, in contact with the third insulating layer in the contact hole and connected electrically to the upper surface of the contact region of the first wiring layer.
REFERENCES:
patent: 3801880 (1974-04-01), Harada et al.
patent: 3839111 (1974-10-01), Ham
patent: 4242698 (1981-12-01), Ghate et al.
RCA Technical Note, "Silicon Nitride Isolation of Phosphosilicate Glass Layer", TN #1234, Nov. 1979.
IBM Technical Disclosure Bulletin, vol. 16, #7, Dec. 1973, "Power Distribution for Large Scale Integrated Circuits" by Braen.
IBM Tech. Disc. Bull., vol. 18, #5, Oct. 1975 by Hayunga, p. 1448.
IBM Tech. Disc. Bull., vol. 19, #6, Nov. 1976 by Tsang, p. 2047.
IBM Tech. Disc. Bull. vol. 24, #3, Aug. 1981 by Rathore, p. 1739.
IBM Tech. Disc. Bull., vol. 22, #7, Dec. 1979 by Eames.
Amano Haruo
Goto Hideto
James Andrew J.
NEC Corporation
Prenty Mark
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