Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1997-11-05
2001-08-14
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S382000, C438S622000, C438S624000
Reexamination Certificate
active
06274452
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority of prior Japanese Patent Application No. 8-293975 filed on Nov. 6, 1996, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer interconnection structure with a thin film resistor and a method for manufacturing the same.
2. Related Arts
Some integrated circuits of semiconductor devices include thin film resistors formed on insulating layers as disclosed in, for example, JP-A-2-58259, JP-A-5-175428, and U.S. Pat. No. 5,382,916. Such thin film resistors are made of CrSi system material, NiCr system material or the like. Specifically, a thin film resistor made of CrSi system material (CrSi, CrSiN, or the like) has advantages such that the resistor can be easily formed in processes for manufacturing the semiconductor device, the resistor can have a resistance in a wide range including a low resistance and a high resistance, and the like. Further, a ratio of change in resistance of the CrSi system resistor can be controlled to be a positive or negative constant value or zero at a temperature within a range where the semiconductor device is generally used, by controlling a compositional ratio of the resistor or conditions of heat treatment performed on the resistor. Because of these reasons, the CrSi system resistor is noticed as a circuit element capable of being employed for various applications.
Conventional processes for forming such a thin film resistor made of CrSi that is applied to a semiconductor integrated circuit for a metal oxide semiconductor field effect transistor (MOSFET) as an example are shown in
FIGS. 1
to
4
.
FIG. 1
shows a state where an FET region
2
is provided on a silicon substrate
1
by a transistor formation process. In this state, a source region
3
is formed in a surface portion of the FET region
2
to have a junction depth xj of, for example, approximately 0.45 &mgr;m. Further, a local oxidation of silicon (LOCOS) layer
4
, a gate oxide layer
5
, a gate electrode
6
made of polysilicon, and a borophosphosilicate glass (BPSG) layer
7
are formed on the silicon substrate
1
. Further, a contact hole
7
a
is formed in the BPSG layer
7
to expose the source region
3
by a wet etching treatment. Then, a CrSi layer
8
a
that is intended to be a thin film resistor
8
and a TiW layer
9
a
that is intended to be a barrier metal layer
9
are formed on an entire surface of the substrate
1
.
Next, as shown in
FIG. 2
, the TiW layer
9
a
and the CrSi layer
8
a
are individually etched by a wet etching treatment and a dry etching treatment using photo resist
10
as a mask. As a result, the thin film resistor
8
and the barrier metal layer
9
are formed on the BPSG layer
7
. During the dry etching treatment for the CrSi layer
8
a
, the surface portion of the silicon substrate
1
exposed from the contact hole
7
a
is etched. The etched depth of the silicon substrate
1
is approximately 10 &mgr;m to 20 &mgr;m.
Subsequently, as shown in
FIG. 3
, after the photo resist
10
is removed, a TiN layer
11
that is intended to be a barrier metal layer and a AlSiCu layer
12
that is intended to be a first Al layer (a first aluminum wiring) are formed and are patterned through a photo resist layer
13
serving as a mask by a dry etching treatment. This dry etching treatment utilizes a reactive ion etching (RIE) technique. During this etching treatment, the barrier metal (TiW layer)
9
prevents the thin film resistor
8
from being etched.
Next, as shown in
FIG. 4
, the TiW layer
9
except portions underlying the first Al layer
12
is removed by a wet etching treatment. Thereafter, the photo resist layer
13
is removed. Then, the processes for forming the thin film resistor
8
and the first Al layer are completed. The TiW layer
9
left between the first Al layer
12
and the thin film resistor
8
can prevent diffusion between the thin film resistor
8
and the first Al layer
12
to prevent deterioration of resistance characteristics of the thin film resistor
8
. However, when the TiW layer
9
is etched, over-etching is usually performed to prevent the TiW layer
9
from remaining. This over-etching is likely to cause under-cut of the TiW layer
9
underlying the first Al layer
12
as indicated by arrows A in FIG.
4
.
SUMMARY OF THE INVENTION
In addition to the above-mentioned problems, requirements for miniaturization and high density integration of an element in recent years accompany a shallow junction (pn junction) of a diffusion layer and fine processing of Al wiring. The fine processing of Al wiring further requires plasma having a high density in a dry etching treatment. To obtain a high integrated density suitable for producing the microcomputer, a wiring width and an opening width of a wiring pattern are limited to be respectively and approximately 1 &mgr;m. The pn junction depth xj is also limited to be approximately 0.15 &mgr;m.
To comply with these requirements, the inventors of the present invention have studied a method for forming a thin film resistor on a semiconductor integrated circuit device based on the above-mentioned design rule (0.8 &mgr;m rule). The studied processes will be explained referring to
FIGS. 5
to
8
. In this experiment, a source region
15
was formed in a surface region of the substrate
1
to form a pn junction having a depth xj of approximately 0.15 &mgr;m in place of the source region
3
in
FIGS. 1
to
4
and a scale in a horizontal direction in
FIGS. 5
to
8
is set to be approximately one fifth of that in
FIGS. 1
to
4
. The other constitutions in
FIGS. 5
to
8
are substantially the same as those shown in
FIGS. 1
to
4
. Explanations similar to those described above referring to
FIGS. 1
to
4
will be omitted.
FIG. 5
corresponding to
FIG. 1
shows a state where the CrSi layer
8
a
serving as the thin film resistor
8
and the TiW layer
9
a
serving as the barrier metal
9
were formed on the BPSG layer
7
. In this case, after the contact hole
7
a
was formed in the BPSG layer
7
, a reflow treatment was performed at a temperature of approximately 900° C.-950° C.
Next, as shown in
FIG. 6
, the TiW layer
9
a
and the CrSi layer
8
a
were etched by a dry etching treatment through the photo resist
10
. At that time, the surface of the silicon substrate
1
exposed from the contact hole
7
a
was simultaneously etched so that the etched depth was approximately 10 nm to 20 nm. As a result, the pn junction depth xj of the source region being approximately 0.15 &mgr;m was reduced by the etched depth.
Next, after the barrier metal layer
11
was formed, Al/TiN/Ti layers for serving as a first Al layer
112
were deposited by a sputtering method, and were patterned by an electron cyclotron resonance (ECR) dry etching treatment using photo resist as a mask, resulting in a state shown in FIG.
7
. The reason why the ECR dry etching treatment was employed is because the ECR dry etching treatment can provide plasma having a high density by a low etching pressure, which can provide fine processing complying with the 0.8 &mgr;m rule. However, by performing the ECR dry etching treatment, not only the first Al layer
112
but also the exposed portion of the barrier metal
9
on the thin film resistor
8
was etched. Therefore, there occur some cases that the barrier metal
9
is removed to expose the thin film resistor
8
made of CrSi so that the thin film resistor
8
is also etched.
Next, as shown in
FIG. 8
, after a plasma silicon nitride (P-SiN) layer
16
was formed, a part of the P-SiN layer
16
formed on the thin film resistor
8
was removed by the etching treatment utilizing a photo-lithography technique. Successively, the TiW layer
9
serving as the barrier metal was removed by a wet etching treatment, so that the process for forming the thin film resistor were completed.
As the result of the above-mentioned experiment, the following
Miura Shoji
Shiraki Satoshi
Soga Hajime
Brophy Jamie L.
Denso Corporation
Meier Stephen D.
Pillsbury & Winthrop LLP
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