Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-09-05
2004-02-10
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S777000, C257S778000, C257S788000, C257S787000
Reexamination Certificate
active
06690089
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device called a lead frame type MCP (Multi-Chip Package), wherein a plurality of semiconductor elements are mounted in one package and sealed with an encapsulating resin.
In a conventional MCP type semiconductor device, a first semiconductor chip or element is bonded to a chip mounting pad and inner lead portions of lead frames by virtue of a semiconductor element adhesive composed of an epoxy resin or the like. Bonding electrodes provided on the first semiconductor element are connected to their corresponding inner lead portions by first metal wires. Further, a second semiconductor chip or element is connected to the inner lead portions through solder balls. The first semiconductor element, the second semiconductor element, the inner lead portions and the respective connecting portions are sealed with a mold resin.
Bonding electrodes on the second semiconductor element are arranged with pitches ranging from about 80 &mgr;m to 200 &mgr;m. In order to connect the inner lead portions and the second semiconductor element, there is a need to set arraying pitches of the inner lead portions in a manner similar to the above (i.e. at pitches ranging from about 80 &mgr;m to 200 &mgr;m). However, a pitch of each inner lead portion is greater than about 180 &mgr;m. This is because of criteria of stable machining of each inner lead portion. Therefore, there are developed unmountable inner lead portions depending on the pitches of the bonding electrodes on the second semiconductor element. Thus, there were restrictions on applicable semiconductor elements. Namely, a problem arose in that the second semiconductor element having the bonding electrodes, whose arraying pitches were each about 180 &mgr;m or less, could not be mounted.
Since the inner lead portions are separated from one another, they easily deform due to vibrations developed during an assembly process and come into contact with an assembly device or the like. Therefore, there was a case in which tip pitches of the inner lead portions were mis-registered with regard to the bonding electrodes on the second semiconductor element so that the inner lead portions and the bonding electrodes could not be connected.
Since the inner lead portions become non-uniform in height when they are deformed due to a reason similar to the above, there was a case in which a failure in connection of the second semiconductor element was encountered. Namely, there existed wide and narrow intervals between the inner lead portions and the second semiconductor element such that the solder balls and the inner lead portions were not brought into contact with the second semiconductor element at locations thereof separated from the inner lead portions by the wide interval, thereby causing failures in their connections.
Furthermore, since there is a need to connect bonding electrodes on the first semiconductor element and bonding electrodes on the second semiconductor element to the same inner lead portions, respectively (to share the use of the inner lead portions), only semiconductor elements having same pin assignments, or completely same semiconductor elements utilized in combination, could be mounted, such that scope of application of products was restricted.
SUMMARY OF THE INVENTION
The present invention provides a novel and improved semiconductor device capable of preventing deviations in pitch during an assembly process of semiconductor elements and inner lead portions to thereby prevent failures in their connections, thus making it possible to enhance reflow packaging of the semiconductor device and connection reliability relative to external thermal stress (change in temperature) subsequent to packaging of the semiconductor device. The present invention also provides a manufacturing method of the semiconductor device.
A semiconductor device of the present invention includes a first semiconductor element provided with bonding electrodes at predetermined widths, and lead frames provided on the first semiconductor element which work as electrical inputs/outputs. The semiconductor device further includes a substrate provided on the lead frames that is provided with metal wirings having a predetermined pitch, and a second semiconductor element provided on the substrate and provided with bonding electrodes having substantially the same pitch as the metal wirings. The semiconductor device further includes solder balls for respectively electrically connecting the bonding electrodes provided on the second semiconductor element and the metal wirings provided on the substrate, first metal wires for respectively electrically connecting the bonding electrodes provided on the first semiconductor element and the lead frames, and second metal wires for respectively electrically connecting the metal wirings provided on the substrate and the lead frames.
REFERENCES:
patent: 4763188 (1988-08-01), Johnson
patent: 5471369 (1995-11-01), Honda et al.
patent: 6072243 (2000-06-01), Nakanishi
patent: 6316822 (2001-11-01), Venkateshwaran et al.
patent: 2002/0153600 (2002-10-01), Chang et al.
patent: 07-030051 (1995-01-01), None
Flynn Nathan J.
Mandala Jr. Victor A.
Oki Electric Industry Co. Ltd.
Wenderoth , Lind & Ponack, L.L.P.
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