Semiconductor device having MOS transistor and a sidewall with a

Details Semiconductor device having MOS transistor and a sidewall with a Semiconductor device having MOS transistor and a sidewall with a

1992-09-04

1993-11-02

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

257324, 257369, 257392, 257408, 257410, 257411, 257639, 257640, 257641, H01L 2702, H01L 2934

Patent

active

052586456

ABSTRACT:
A semiconductor device including a semiconductor substrate with a P-type well formed in the semiconductor substrate and a gate insulator layer formed on the semiconductor substrate. N-type diffusion regions are formed in the P-type well on both sides of the gate insulator layer. A gate electrode is formed on the gate insulator layer, where the gate electrode has top and side surfaces. The gate electrode and the N-type diffusion regions respectively form gate, source and drain of a N-channel MOS transistor. An insulating layer covers a portion of the N-type diffusion regions, the side surfaces of the gate electrode and at least a portion of the top surface of the gate electrode. The side wall layer which is made of an insulating material is formed on the insulating layer to provide a smooth coverage around the side of the gate electrode and aligns with an edge of said insulating layer which stops covering the N-type diffusion regions.

REFERENCES:
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Mizuno et al., "Si.sub.3 N.sub.4 /SiO.sub.2 Spacer Induced High Reliability in LDDMOSFET and Its Simple Degradation Model", IEDM 88, 1988 pp. 234-237.

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