Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Reexamination Certificate
2000-08-21
2004-02-17
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
C257S566000, C257S565000, C438S357000
Reexamination Certificate
active
06693344
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device having low and high breakdown voltage transistors.
2. Description of the Prior Art
A semiconductor device comprising transistors employed for driving/controlling a motor or an air bag for a car, for example, is described as an exemplary conventional semiconductor device. In this type of semiconductor device, low and high breakdown voltage bipolar transistors and a CMOS (complementary metal oxide semiconductor) transistor are formed on the same semiconductor substrate.
The low and high breakdown voltage bipolar transistors are described with reference to the structure of the semiconductor device, and the low and high breakdown voltage bipolar transistors and the CMOS transistor are described with reference to a method of fabricating the semiconductor device.
FIG. 25
is a schematic sectional view showing the structure of a conventional semiconductor device. Referring to
FIG. 25
, both low and high breakdown voltage npn bipolar transistors are formed on regions of a p-type silicon substrate
109
electrically isolated from the remaining elements by p
+
diffusion layers
110
and
111
. Each of the low and high breakdown voltage npn bipolar transistors has a collector
108
, a base
103
a
or
103
b
and an emitter
104
.
In the low breakdown voltage npn bipolar transistor, the collector
108
has an n
+
diffusion layer
105
formed on the p-type silicon substrate
109
, an n
−
epitaxial layer
106
formed on the p-type silicon substrate
109
, and an n
−
diffusion layer
107
a
and an n
+
diffusion layer
107
b
formed on the surface of the n
−
epitaxial layer
106
. The base
103
a
has a p-type diffusion layer
130
formed on the surface of the n
−
epitaxial layer
106
and a p
+
diffusion layer
102
b
formed on the surface of the p-type diffusion layer
130
. The emitter
104
has an n
−
diffusion layer
104
a
and an n
+
diffusion layer
104
b
formed on the surface of the p-type diffusion layer
130
.
Field oxide films
112
are selectively formed to electrically isolate the base
103
a
, the emitter
104
and the collector
108
from each other. In a region of the low breakdown voltage npn bipolar transistor held between the p
+
diffusion layer
102
b
and the emitter
104
, however, no field oxide film
112
is formed on the surface of the p-type diffusion layer
130
.
In the high breakdown voltage npn bipolar transistor, the base
103
b
has a p
+
diffusion layer
102
a
formed on the surface of the n
−
epitaxial layer
106
in a larger diffusion depth than the p-type diffusion layer
130
, a p
+
diffusion layer
102
b
formed on the surface of the p
+
diffusion layer
102
a
and a p
+
diffusion layer
101
enclosing the lower portions of the emitter
104
and the p
+
diffusion layer
102
b.
Field oxide films
112
are formed on the p
+
diffusion layers
101
and
102
a
held between the p
+
diffusion layer
102
b
and the emitter
104
.
The remaining structure of the high breakdown voltage npn bipolar transistor is substantially identical to that of the low breakdown voltage npn bipolar transistor, and hence components of the high breakdown voltage npn bipolar transistor identical to those of the low breakdown voltage npn bipolar transistor are denoted by the same reference numerals, not to repeat redundant description.
An interlayer isolation layer
113
is formed to cover the low and high breakdown voltage npn bipolar transistors, and electrodes
114
are formed to be electrically connected with the collectors
108
, the bases
103
a
and
103
b
and the emitters
104
respectively.
A method of fabricating the conventional semiconductor device is now described.
FIGS. 26
to
30
are schematic sectional views successively showing steps in the method of fabricating the conventional semiconductor device. Referring to
FIG. 26
, the n
−
epitaxial layer
106
is formed on the p-type silicon substrate
109
through the n
+
diffusion layers
105
and the p
+
diffusion layers
110
.
Referring to
FIG. 27
, an n
−
diffusion layer
122
is formed on a CMOS transistor region, followed by formation of the p
+
diffusion layers
102
a
and the p
−
diffusion layers
111
for element isolation.
Thereafter the field oxide films
112
are selectively formed on the surface of the substrate
109
by a general LOCOS (local oxidation of silicon) method. Thereafter boron ions are selectively implanted thereby forming the p
+
diffusion layers
101
in the p
+
diffusion layers
102
a
and
111
.
Thin oxide films
121
are formed on portions of the surface of the substrate
109
formed with no field oxide films
112
.
Referring to
FIG. 28
, gate electrodes consisting of films
123
of polycrystalline silicon (hereinafter referred to as doped polysilicon) doped with an impurity and tungsten silicide films
124
are formed on the CMOS transistor region. Thereafter the p-type diffusion layer
130
is formed on the low breakdown voltage npn bipolar transistor region. Further, the n
−
diffusion layers
104
a
and
107
a
and n
−
diffusion layers
125
a
are formed on the respective transistor regions.
Referring to
FIG. 29
, a silicon oxide film (not shown) is formed to cover the overall surface and the overall surface of this silicon oxide film is thereafter anisotropically etched for forming side wall insulating layers
126
covering the side surfaces of the gate electrodes
123
and
124
. The thin silicon oxide films
121
are removed from the portions formed with no field oxide films
112
by the anisotropic etching for forming the side wall insulating layers
126
, for partially exposing the surface of the substrate
109
.
In this state, the n
+
diffusion layers
104
b
and
107
b
and n
+
diffusion layers
125
b
are formed on the respective transistor regions. In order to form these n
+
diffusion layers
104
b
,
107
b
and
125
b
, arsenic is implanted into prescribed regions of the semiconductor substrate
109
and thereafter heat treatment is performed at a temperature of 900° C. Thereafter the p
+
diffusion layers
102
b
are formed on the low and high breakdown voltage npn bipolar transistor regions, and p
+
diffusion layers
127
for defining source/drain regions are formed on the CMOS transistor region.
Referring to
FIG. 30
, the interlayer isolation layer
113
is formed to cover the overall surface, and thereafter the electrodes
114
are formed in contact with the respective diffusion layers.
In the aforementioned semiconductor device, the current amplification factor h
FE
characteristic of the low breakdown voltage npn bipolar transistor remarkably disperses in the wafer plane, and the fabrication steps are disadvantageously complicated. These problems are now described.
The inventors have evaluated collector current I
C
dependency of the current amplification factor h
FE
as to the conventional low breakdown voltage npn bipolar transistor. It has consequently been proved that the current amplification factor h
FE
remarkably disperses in the wafer plane.
FIGS. 31B
to
31
F show the results.
FIGS. 31B
to
31
F are graphs showing the results evaluated on five measuring points
1
to
5
in the wafer plane shown in
FIG. 31A
respectively. It is understood from these graphs that the values of the current amplification factor h
FE
for a specific collector current I
C
vary and disperse in the wafer plane.
The current amplification factor h
FE
is defined as the ratio (I
C
/I
B
) of the collector current I
C
to a base current I
B
. In order to investigate the cause for such dispersion of the current amplification factor h
FE
, base-to-emitter voltage V
EB
dependency of the collector current I
C
and base-to-emitter voltage V
EB
dependency of the base cur
Onoda Hiroshi
Sato Kimitoshi
Yamamoto Fumitoshi
Yamashita Yasunori
Nadav Ori
Renesas Technology Corp.
LandOfFree
Semiconductor device having low and high breakdown voltage... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having low and high breakdown voltage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having low and high breakdown voltage... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3298217