Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive...
Reexamination Certificate
2007-09-18
2010-11-09
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
C438S424000, C257S706000, C257S506000, C257SE21546
Reexamination Certificate
active
07829429
ABSTRACT:
One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate.
REFERENCES:
patent: 6800518 (2004-10-01), Bendernagel et al.
patent: 6818528 (2004-11-01), Mandelman et al.
patent: 7015147 (2006-03-01), Lee et al.
patent: 7018882 (2006-03-01), Tweet et al.
patent: 7078298 (2006-07-01), Lee et al.
patent: 7452784 (2008-11-01), Henson et al.
http://legwww.epfl.ch/leg2/cours—nano—06/Cours4—Master—Nanoelectronic s—0607.pdf, 14 pages, 2004 Adrian Ionescu.
Silicon MOSFETs-Novel Materials and Alternative Concepts, 2 pages, no name/year, pp. 380-381.
Malgorzata Jurczak et al., “Silicon-on-Nothing (SON)-an Innovative Process for Advanced CMOS,” IEEE Transactions on Electron Devices, vol. 47, No. 11, Nov. 2000, pp. 2179-2187.
M. Jurczak et al., “SON (Silicon on Nothing)-A New Device Architecture for the ULSI Era,” 1999 Symposium on VLSI Technology Digest of Technical Papers, pp. 29-30.
Tsutomu Sato et al., “Fabrication of Silicon-on-Nothing Structure by Substrate Engineering Using the Empty-Space-in-Silicon Formation Technique,” Japanese Journal of Applied Physics, vol. 43, No. 1, 2004, pp. 12-18.
Phillip E. Thompson et al., “Vertical SiGe-based silison-on-nothing (SON) technology for sub-30 nm MOS devices,” Materials Science in Semiconductor Processing 8 (2005), pp. 51-57.
S. Monfray et al., “Emerging silicon-on-nothing (SON) devices technology,” Solid-State Electronics 48 (2004), pp. 887-895.
G. K. Celler, “Frontiers of silicon-on-insulator,” Journal of Applied Physics, vol. 93, No. 9, May 1, 2003, pp. 4955-4978.
I.Z. Mitrovic et al., “Review of SiGe HBTs on SOI,” Solid-State Electronics 49 (2005), pp. 1556-1567.
Christophe Maleville et al., “Smart-Cut technology: from 300 mm ultrathin SOI production to advanced engineered substrates,” Solid-State Electronics 48 (2004), pp. 1055-1063.
Labonte Andre P.
Printy Craig
Ramdani Jamal
National Semiconductor Corporation
Trinh Michael
LandOfFree
Semiconductor device having localized insulated block in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having localized insulated block in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having localized insulated block in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4162046