Semiconductor device having leadless package structure

Details Semiconductor device having leadless package structure Semiconductor device having leadless package structure

2002-02-25

2004-03-30

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Outside periphery of package having specified shape or...

C257S433000, C257S670000, C257S787000, C257S621000

Reexamination Certificate

active

06713868

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-367482, filed Nov. 30, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a resin-sealed semiconductor device having a leadless package structure.
2. Description of the Related Art
Leadless packaging of semiconductor devices has recently been advanced in order to meet the requirements for miniaturizing a portable terminal. A ceramic substrate employs an end-face through hole structure in which a through hole is formed in the end face of the substrate. The employment of the end-face through hole structure is common as a matter of solderability.
In order to manufacture semiconductor devices at low cost, plastic packaging for sealing a chip with resin is under consideration. Especially a resin printing method using liquid resin is predominant over a prior art transfer molding method. This is because an expensive mold is unnecessary and thus a reduction in cost can be accomplished.
However, if a substrate having an end-face through hole structure is sealed by the resin printing method, the following problem will occur. As shown in
FIG. 12
, resin
18
enters a through hole
51
from its opening portion and blocks an end-face electrode
13
.
If an LGA (Land Grid Array) system not using an end-face through hole but using a normal via hole
61
is adopted as illustrated in
FIGS. 13
to
15
, it is the most suitable for a resin sealing process because the above problem does not occur. In the LGA system, however, an operator cannot visually check a degree of rising of solder after a motherboard is soldered. Such a solderability problem occurs.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to an aspect of the present invention comprises: a substrate; a semiconductor chip arranged on the substrate; a first electrode formed in the substrate and connected to the semiconductor chip; a concave portion provided on a side of the substrate, the concave portion extending from a back of the substrate and terminating in the substrate, and at least part of the first electrode being exposed to the concave portion; and a metal layer formed on the at least part of the first electrode.


REFERENCES:
patent: 5741729 (1998-04-01), Selna
patent: 5752182 (1998-05-01), Nakatsuka et al.
patent: 6301122 (2001-10-01), Ishikawa et al.
patent: 6383835 (2002-05-01), Hata et al.
patent: 6399415 (2002-06-01), Bayan et al.

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