Semiconductor device having layered electrode

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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Details

257763, 257764, 257766, 257432, 257466, H01L 310224, H01L 310232, H01L 22482, H01L 2940

Patent

active

054122490

ABSTRACT:
An n.sup.- -type InP buffer layer is formed on an n-type InP substrate. An n.sup.- -type InGaAs light absorbing layer is formed on the n.sup.- -type InP buffer layer. An n.sup.- -type InP cap layer is formed on the n.sup.- -type InGaAs light absorbing layer. A p-type InP region is formed in the InP cap layer. A layered electrode having a contact with the p-type InP region comprises a first layer made of an Au layer, a second layer made of a Ti layer or the like, a third layer made of a Pt layer or the like, and a fourth layer made of an Au layer. The first layer made of Au has a thickness of 1 to 500 nm. This structure improves an ohmic ability and a peel strength at a contact portion where an electrode is connected, and simplifies manufacturing steps.

REFERENCES:
patent: 5047832 (1991-09-01), Tonai
patent: 5077599 (1991-12-01), Yano et al.
patent: 5260603 (1993-11-01), Kamura
Boos et al., The Addition of Ni in AuZn Gate Ohmic Contacts for lnP Field Effect Transistors, J. Vac. Sci. Technol. B, vol. 7, No. 3, May/Jun. 1989, pp. 502-504.

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