Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-01-04
2011-01-04
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230040, C365S230060
Reexamination Certificate
active
07864623
ABSTRACT:
A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits sequentially shifting the normal-phase (reverse-phase) command signal based on the normal-phase (reverse-phase) clock, a selector circuit controlling a signal path so that the normal-phase (reverse-phase) command signal is transmitted through the first (second) counter circuit when an even latency is set and the normal-phase (reverse-phase) command signal is transmitted so as to be shifted from the first (second) counter circuit to the second (first) counter circuit when an odd latency is set, and a control circuit controlling so that the latch circuits of the first (second) counter circuit are activated in response to the input command signal and stopped after an operation period is elapsed.
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Fujisawa Hiroki
Kinoshita Hiroto
Elpida Memory Inc.
Nguyen Tuan T.
Sughrue & Mion, PLLC
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