Semiconductor device having latency counter

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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Details

C365S230040, C365S230060

Reexamination Certificate

active

07864623

ABSTRACT:
A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and second counter circuits each including latch circuits sequentially shifting the normal-phase (reverse-phase) command signal based on the normal-phase (reverse-phase) clock, a selector circuit controlling a signal path so that the normal-phase (reverse-phase) command signal is transmitted through the first (second) counter circuit when an even latency is set and the normal-phase (reverse-phase) command signal is transmitted so as to be shifted from the first (second) counter circuit to the second (first) counter circuit when an odd latency is set, and a control circuit controlling so that the latch circuits of the first (second) counter circuit are activated in response to the input command signal and stopped after an operation period is elapsed.

REFERENCES:
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patent: 7177231 (2007-02-01), Johnson et al.
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patent: 7580321 (2009-08-01), Fujisawa et al.
patent: 7624225 (2009-11-01), Gower et al.
patent: 2007/0091714 (2007-04-01), Fujisawa et al.
patent: 2007-115351 (2007-05-01), None

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