Semiconductor device having isolating regions

Details Semiconductor device having isolating regions Semiconductor device having isolating regions

1994-02-25

1997-07-08

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

257315, 257397, 257398, 257399, G11C 1134

Patent

active

056468881

ABSTRACT:
Disclosed is a semiconductor memory device which has memory cell transistors each comprising a liner source diffusion layer, a land-shaped drain diffusion layer, a gate oxide film containing a floating gate formed on the channel region between those diffusion layers, and a control gate formed on the gate oxide film. Trenches are formed in the substrate in no contact with the channel regions to isolate the cell transistors from each other.

REFERENCES:
patent: 4698900 (1987-10-01), Esquivel
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 5278438 (1994-01-01), Kim et al.
patent: 5321288 (1994-06-01), Gill et al.
IEDM Technical Digest, p. 583, Dec. 1989, Yosiaki S. Hisamune, et al., "A 3.6 .mu.m.sup.2 Memory Cell Structure for 16MB EPROMS".

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