Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
2002-06-20
2003-11-11
Tran, Thien (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S501000, C257S503000, C257S505000, C257S506000, C257S508000, C257S513000, C257S520000
Reexamination Certificate
active
06646319
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, a circuit in which is isolated and insulated by an isolating region.
2. Description of the Related Art
A semiconductor device shown in
FIG. 10A
is proposed. In the proposed device, an SOI substrate
200
includes a base silicon layer
200
b
, an active silicon layer
200
c
, and an insulating layer
200
a
that separates the silicon layers
200
b
,
200
c
, as shown in FIG.
10
B. The active silicon layer
200
c
includes a power device area S, where an output power device such as a UPDRAIN or an LDMOS is located, and an on-chip circuit area T, where an on-chip circuit that generates reference voltage is located. The power device area S is surrounded by a trench
200
d
and an insulating material
201
a
, which is located in the trench
200
d
. The on-chip circuit area T is surrounded by another trench
200
e
and another insulating material
201
b
, which is located in the trench
200
e
surrounding the on-chip circuit area T.
The active silicon layer
200
c
includes a plurality of n
+
-type contact regions
202
between the power device area S and the on-chip circuit area T to fix the potential, as shown in
FIGS. 10A and 10B
.
The active silicon layer
200
c
also includes a field ground (F/G) area
203
. The field ground area
203
and each n
+
-type contact region
202
are electrically connected by a wiring line
204
.
In the proposed device, the output power device and the on-chip circuit are insulated and electrically separated from each other by the insulating layer
200
a
and the insulating materials
201
a
,
201
b
, as shown in FIG.
10
B. However, when the output power device is switched with relatively high frequency, an electrical noise is generated due to the variation in counter-electromotive force or load current generated by inductive load (L load) in the output power device. The noise can prevent the on-chip circuit from functioning properly. The influence of the noise can be attenuated by increasing the distance between the output power device and the on-chip circuit. However, the size of the SOI substrate
200
increases.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above aspects with an object to provide a semiconductor device having a structure, with which the influence of an electrical noise, which is generated by an output power device, on an on-chip circuit is suppressed.
In the present invention, the output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise, which is generated by the output power device, is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.
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patent: 5480832 (1996-01-01), Miura et al.
patent: 5557134 (1996-09-01), Sugisaka et al.
patent: 5559356 (1996-09-01), Yukawa
patent: 5644157 (1997-07-01), Iida et al.
patent: 5793060 (1998-08-01), Morikawa
patent: 6104078 (2000-08-01), Iida et al.
patent: 6429502 (2002-08-01), Librizzi et al.
patent: 2002/0014639 (2002-02-01), Imai et al.
patent: A-7-302914 (1995-11-01), None
patent: A-2000-208714 (2000-07-01), None
patent: A-2001-15589 (2001-01-01), None
patent: A-2002-33382 (2002-01-01), None
Ban Hiroyuki
Itakura Hirokazu
Denso Corporation
Posz & Bethards, PLC
Tran Thien
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