Semiconductor device having interlayer insulator and method...

Details Semiconductor device having interlayer insulator and method... Semiconductor device having interlayer insulator and method...

1997-08-01

2001-05-15

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S760000, C257S649000, C257S640000

Reexamination Certificate

active

06232663

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to highly integrated semiconductor devices (IC or LSI) having an interlayer insulator. In particular, the present invention is directed to a technique for acquiring a higher reliability interlayer insulator (inter metal dielectric) and an improvement in forming via contact holes in a semiconductor device.
2. Description of the Related Art
Commonly, conductive layers of semiconductor devices have been fabricated with the following method. An interlayer insulator is deposited on the surface of a patterned metal interconnect. Via contact holes are opened into the interlayer insulator by anisotropic etching to expose the metal interconnect at the bottom of the via contact holes. An aluminum-containing conductive material is then deposited over the interlayer insulator, also filling the inside of the via contact holes. Quite frequently, the electrical connection between one metal layer and another metal area is formed by the above described method.
Recently, 64M bit DRAMs, 256M bit DRAMs, and higher integrated circuits have appeared. However, while the density of semiconductor devices is increasing, semiconductor fabricating processes still employ a conventional conductive layer forming method, such as the method stated above. In the conventional method, the aluminum containing conductive material is very likely to be easily cut at an edge or bottom portion of the via contact hole during the fabricating process or during normal use, due to its thinner aluminum formation. Isotropic etching, followed by an anisotropic etching step, is frequently used as a solution to this problem by opening a via contact hole so as to make a gentle slope near the edge of a via contact hole. Such a contact hole opening technique is disclosed in detail in Japanese Laid-open Patent Sho 56-90523 and its counterpart U.S. Pat. No. 4,352,724.
When adopting the above-identified contact hole opening technique (hereinafter called isotropic-anisotropic etching), a wet etchant is conventionally used for the isotropic etching step. On the other hand, the interlayer insulator to be isotropically etched is frequently formed by a chemical vapor deposition (CVD) method. The reason for using the CVD method is that a CVD produced insulator will ordinarily have enough quality to seal off wafer vapors from a SOG (Spin on Glass) layer underneath the insulator layer. However, while only an upper CVD insulator layer of a multilayer semiconductor device is to be wet etched, even the lower SOG layer is also frequently etched accidentally by the wet etchant.
FIGS. 13-16
illustrate this etching problem in the prior art.
FIGS. 13-16
illustrate cross-sectional views of a multilayer semiconductor device corresponding to different sequential stages of the conventional fabricating method. As shown in
FIG. 13
, a Spin on Glass (SOG) layer
2
is coated over a Plasma Enhanced CVD (PE-CVD) SiON liner
11
, and the coated SOG layer
2
is baked so as to melt and flow. A Plasma Enhanced CVD (PE-CVD) oxide film
3
is formed over the surface of the SOG layer
2
. A photoresist
4
having an opening pattern is formed over the surface of the PE-CVD oxide film
3
.
In the chemical vapor deposition step to form the PE-CVD oxide film
3
, start/stop timing of various gas flow and turning on/off RF (radio frequency) power are depicted in FIG.
17
.
FIG. 17
shows the timing sequences between four processes, from a start/stop timing of N
2
O gas flow and a start/stop timing of RF power to a start/stop timing of SiH
4
(monosilane) gas flow at MFC (i.e., at a gas valve) and in-chamber.
FIG. 17
shows that these four processes listed along the ordinate axis alter in accordance with time along the abscissa axis. First, N
2
O gas flow is turned on, followed by RF power being turned on to generate gaseous plasma, SiH
4
(monosilane) gas flow is next turned on at MFC, and lastly, SiH
4
gas is introduced into a CVD chamber. When ending this CVD step, each of these processes (i.e., the top three processes) are turned off in reverse order, as shown in FIG.
17
. The timing sequence of the SiH
4
gas flow in-chamber, depicted on the bottom of
FIG. 17
, mirrors the SiH
4
gas flow at MFC because the SiH
4
gas flow in-chamber is the same SiH
4
gas flow at MFC, but merely separated by a small time differential &Dgr;t for the SiH
4
gas to travel into the chamber from the gas valve.
FIG. 13
shows the cross-sectional view of the multilayer semiconductor device at a state just after wet etching of the PE-CVD oxide film
3
through an opening of the photoresist
4
. When depositing the PE-CVD oxide film
3
, string-like defects
61
stretching from defect nucleic
62
are formed in accordance with the thickness of the deposited PE-CVD oxide film
3
. If the string-like defects
61
appear on or near an isotropic etched surface of the PE-CVD oxide film
3
(such as string-like defects
63
), then the wet etchant may penetrate the SOG film
2
through the string-like defects
63
. As a result of this penetration into the SOG film
2
, the SOG film
2
is very often accidentally etched, creating many bubble-like defects
70
near the surface of the SOG film
2
.
Following the above-mentioned steps, a portion of the surface of the metal interconnect
10
is exposed using anisotropic etching through photoresist mask
4
along a dotted line portion of the semiconductor device depicted in FIG.
14
. Typically, Reactive Ion Etching (RIE) is adopted for the anisotropic etching.
FIG. 15
shows a cross sectional view of the semiconductor device in a state just after the contact hole opening anisotropic etching step, exposing a portion of the metal interconnect
10
surface. If the wet etched bubble-like defects
70
in the SOG film
2
are relatively large, voids
71
are left in the SOG film
2
. Moreover, the uneven thickness of the SOG film
2
resulting from the bubble-like defects
70
may also lead to excessive etching in some portions of the via hole, damaging corresponding portions
72
of the exposed surface of the metal interconnect
10
.
After the above-described via contact hole opening step,
FIG. 16
shows a cross sectional view of the semiconductor device in a state just after a wiring layer
5
is deposited to electrically contact with the metal interconnect
10
surface through the via contact hole. An aluminum alloy is usually used for the wiring layer
5
due to its low electrical resistance. But, since the aluminum alloy or aluminum is, at present, exclusively deposited by a sputtering technique, a coverage profile may be degraded, especially inside the via contact hole having defects
71
and
72
. When the wiring layer
5
is deposited by the sputtering method, the coverage profile of aluminum alloy layer, especially in the contact hole region, may be degraded due to so-called “shadowing effects”. In particular, aluminum alloy species or particles, sputter-deposited at high speeds, are deposited in voids
71
on the inner surface of the via contact hole and in defects
72
on the metal interconnect
10
surface, and migrate about at random as shown in FIG.
16
. Further, the degraded deposited wiring layer
5
can experience migration problems caused by thermal stresses in later steps or by electro migration, resulting in open-circuit failures in the aluminum alloy wiring layer
5
. Thus, degradation of product reliability may result.
Moreover, in using an organic silanol material, such as the Spin On Glass (SOG) film
2
, numerous bubble-like defects
70
and voids
71
may result. Organic silanol material such as the SOG film
2
is used for a lower interlayer insulator mainly because of its ease in formation. For the same reason, Spin On Siloxane (SOS) or Hydrogen Silsesquioxane (HSiO
3/2
)
n
are also suitable for the same purpose. In particular, organic silanol material is easily coatable and can easily planarize the surface of the interlayer insulator. However, such coatable insulating materials are basically fragile and are easily etched because o

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