Semiconductor device having integrated memory and logic

Details Semiconductor device having integrated memory and logic Semiconductor device having integrated memory and logic

2002-12-23

2004-08-31

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S189050, C327S379000

Reexamination Certificate

active

06785187

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor apparatus (including a microcomputer) with a memory and logic circuit integrated into a single chip.
BACKGROUND OF THE INVENTION
A conventional dynamic RAM
1000
is constructed as shown in FIG.
16
and operates according to a timing chart shown in FIG.
17
. More specifically, time t0 to t3 indicates a read cycle and time t3 to t6 indicates a write cycle.
First, the operation of the read cycle of time t0 to t3 will be explained. In the following explanations, a signal that becomes active at an “L” level or an inverted signal is expressed with “/” prefixed to the signal name.
Since a /row enable signal (row enable signal that becomes active at an “L” level) is “L
1
” on the rising edge of a time t0 clock signal, a row address R
0
is latched and output by a D type flip flop (hereinafter referred to as “DFF”) of a row address latch circuit
1002
. A row decoder
1004
starts decoding at a point in time when R
0
is output as the latch data of the above described row address, reads data of a memory cell connected to a word line (hereinafter referred to as “WL”) selected by the decoding result to a bit line or /bit line and amplifies the data using
1024
sense amplifiers.
At time t1, a /row selection control signal is “L” and a /column selection control signal is “L”, and therefore a /column enable signal is driven “L” and a column address C
0
is latched and output by a DFF of a column address latch circuit
1001
on the rising edge of the clock signal.
Decoding starts at a point in time when C
0
is output as the latch data of the above described column address, one of four column selection signals (
3
:
0
) is enabled, 256 bit lines and /bit lines are selected from among the bit lines and /bit lines amplified by the above described
1024
sense amplifiers, amplified by a main amplifier and output to data outputs (
255
:
0
). Next, the operation of the write cycle of time t3 to t6 will be explained.
At time t3, the same operation as that at time t0 is performed, one of WL (
255
:
0
) is selected by R
1
to carry out the same operation as that at time t0, connected to a bit line and /bit line selected by a column address C
1
and data of data inputs (
255
:
0
) is written in memory cells whose WL is enabled.
DISCLOSURE OF THE INVENTION
However, in the conventional configuration, row addresses and column addresses are latched by DFF, decoding of an address is started a certain time after the clock for confirming the DFF address has risen, which lengthens the time after the clock rise until WL is selected and the time after the clock rise until column selection signals (
3
:
0
) are decoded, and lengthens clock cycles of times t0, t1, t3 and t4 necessary for operation, producing a problem that it is not possible to perform read/write at high speed.
It is an object of the present invention to provide a semiconductor apparatus capable of performing read/write at high speed.
To attain this object, a semiconductor apparatus according to a first aspect of the present invention provides a semiconductor apparatus with a memory and logic section integrated into a single chip, characterized in that the logic section outputs m row addresses from 1st to mth addresses and n column addresses from 1st to nth addresses to the memory, the memory is constructed of a memory cell array block provided with an input/output section to/from the logic section and a plurality of memory cells, a latch circuit connected to the logic of the input/output section is connected by a scan chain to perform a scan test to test the connection of the logic section, the input/output section is provided with a row address input section and a column address input section, the row address input section is constructed of m latch circuits from 1st to mth row latch circuits, the column address input section is constructed of n latch circuits from 1st to nth column latch circuits, and in the kth (k: integer 1≦k≦m) row latch circuit, a clock is input to a clock input (CK input), the 1st latch enable signal (1st /latch enable signal) output from the above described memory cell array block is input to an enable signal input (/EN input), the kth row address is input to a data input (D input), an output Q (Q output) is connected to the above described memory cell array block, a shift signal of the above described scan chain data during a scan test is input to a test control signal input (NT input), shift data in a preceding stage of the above described scan chain is input to a test input CDT input), a shift signal to a subsequent stage of the above described scan chain is output to a test output QT (QT output), and in the above described pth (p: integer 1≦p≦n) column latch circuit, a clock is input to a clock input (CK input), the 2nd latch enable signal (2nd /latch enable signal) output from the above described memory cell array block is input to an enable signal input (/EN input), the (p-m)th column address is input to a data input (D input), an output Q (Q output) is connected to the above described memory cell array block, a shift signal of the scan chain data during a scan test is input to a test control signal input (NT input), shift data in the preceding stage of the above described scan chain is input to a test input (DT input) and a shift signal to the subsequent stage of the above described scan chain is output to a test output QT (QT output).
The latch circuit according to a second aspect of the present invention is constructed of three inputs; a clock input (CK input), an enable signal input (/EN input) and a data input (D input), and an output Q (Q output), a data input circuit and a data holding circuit, characterized in that the above described data input circuit is fed the above described clock input (CK input), enable signal input (/EN input) and the above described data input (D input) and outputs (DQ
3
), and when the above described enable signal input (/EN input) is active (“L”) and the above described clock input (CR input) is at the 1st logic level, outputs the inverted level of the above described data input (D input) to the above described (DQ
3
), and when the above described enable signal input (/EN input) is non-active (“H”) or when the above described clock input (CR input) is at the 2nd logic level, holds (DQ
3
) at high impedance, the above described data holding circuit is constructed of an inverter that is fed (A
1
) and outputs the above described (Q output) and an output control circuit, the above described (A
1
) is connected to (DQ
3
), the above described output control circuit has three inputs; the above described output Q (Q output), the above described clock input (CK input) and the above described enable signal input (/EN input), and an output (DO
1
) input to the above described (A
1
), and when the above described enable signal input (/EN input) is non-active (“H”) or the above described clock input (CK input) is at the 2nd logic level, outputs the inverted level of the above described output Q (Q output) to the above described (DO
1
), and when the above described enable signal input (/EN input) is active (“L”) and the above described clock input (CK input) is at the 1st logic level, holds the above described (DO
1
) at high impedance.
The latch circuit according to a third aspect of the present invention is a latch circuit provided with a data input circuit and a data holding circuit, characterized in that the above described data input circuit has three Pch transistors connected in series; a Pch transistor whose gate is connected to an enable signal input (/EN input), a Pch transistor whose gate is connected to a data input (D input) and a Pch transistor whose gate is connected to a clock input (CK input), with one end of the above described Pch transistors connected in series connected to a power supply and the other end connected to the input (A
1
) of the above described data holding circuit, and has three Nch transistors connected in series; an Nch transistor whose gate is connected to (EN) whi

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